Ramesh Dewangan and Bernard Murphy (Atrenta)
EETimes (1/9/2014 02:01 PM EST)
80M gates were a huge design challenge. Now, 22nm and 14nm is around the corner, with design capacities of 500M gates or more. A leading graphics chip boasts 1.4B gates.
Along with size, complexity has also increased dramatically in numbers of clocks, clock domains, and power and voltage domains. The sheer number of IPs and amount of integration logic is amplifying small issues in power, testability, and routing congestion into large problems during assembly. It is no longer practical to rely on detection and cleanup of all these problems during integration. The loop to cycle back through IP suppliers, system architects and others will likely derail an ambitious SoC project.
From an integrator's point of view, primarily three factors determine the quality of the design:
- That all the IP to be used has been fully qualified, prior to integration, especially in the configurations the integrator plans to use
- The ability to quickly assess the quality of the integration, based on the above assumption
- To not have to wade through a blizzard of reports on issues inside IPs (which the integrator is not in a position to address), in order to find one or two potentially real issues at the integration level
This calls for a hierarchical approach to analysis and signoff: IP blocks and subsystems must be fully qualified, in the configurations they will be used, and then abstracted for the purpose of quality and signoff at the SoC level, so the integrator need only see and address those issues unique to the integration.
What does this look like? For an internal block developer and for an IP supplier, the first steps are the same. You need to get to a quantifiable measure of RTL signoff for the target IP.
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