English
Voltage Domain Interfacing Cells for use between power domains using core transistors.
Efficient analysis of CDC violations in a million gate SoC, part 2
Sanymi Gupta , Aniruddha Gupta & Ankush Sethi (Freescale Semiconductor)
EDN (February 03, 2014)
Reset path
One interesting topic of discussion is whether to use synchronous or asynchronous reset in design. In synchronous reset design, we use reset signal in the D path of flop. Hence, the assertion of reset will only effect or reset the state of the flop on the active edge of a clock. In some designs, the reset must be generated by a set of internal conditions. A synchronous reset is recommended for these types of designs because it will filter the logic equation glitches between clocks. But if we have some issues or failure leading to unavailability of clocks then we will not be able to reset/initialize the system. Only an asynchronous reset would work in such a condition. However, we may face metastability issues if de-assertion of this asynchronous reset is not synchronized properly.
Need of de-assertion synchronization for asynchronous reset?
If the asynchronous reset is de-asserted within the setup or hold window of clock of flop then there could be metastability at the flop’s output. So we need to synchronize the de-assertion of reset.
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