Impact of wire resistance in advance technology

Hardik Desai, eInfochips

In new era of chip implementation, designs are becoming more complex and more challenging as technology is shrinking to 28nm and below. In advance technology process, the cell delays got reduced but impact of wire/via resistance becomes more critical than previous nodes as wire width is reducing. The larger wire delay affects transition time and yields poor timing in clock tree cause lower performance in physical implementation.With advance technology such as 28nm and below, the process characteristics become remarkably complex and wiring resistance rapidly increases, which unavoidably means that more sign-off corners and more accurate sign-off and layout tools are required. This article illustrates how wire delay causes skew/timing problems when you are optimizing multi-corner design and how wire resistance can be optimized to achieve best performance during the physical implementation flow.

Multi-corner variation due to wire resistance

While optimizing design for MMMC (Multi mode multi corner), we usually see many discrepancies in timing between different corners. For example considering hold scenario, it is not the case now that meeting design in hold best corners will meet in hold worst with same temperature. In fact we might see more timing violation in hold-worst corner than hold-best.One of the main parameter is wire resistance because slow path in hold-best corner could be faster in hold-worst due to wire delay difference.

Following example shows how large wire resistance produce delay difference between two corners. Consider there are two hold corners in the design working at the same temperature 125 degree centigrade but different voltages being best as 1.2 volts and worst as 1.0 volts.

Figure1: Large wire delay

In Figure 1, the total delay in hold_best corner is 320ps while in hold_worst is 240ps. Even though cell delays are twice in hold_worst, overall delay is less in that corner due to wire resistance. Skew between two corners in this case is 80ps. Wire delay in hold_best is more than hold_worst because hold_best isCbest extraction corner and Cbest is checked with the minimum C and maximum R whilehold_worst is Cworst extraction corner and Cworst is checked with maximum C and minimum R. For smaller nets the effect or R will be small but for longer nets it will be very significant and causes more variation between two corners.Cell delays in hold_worst corner are higher because it is operating with 1.0 volts compare to 1.2 volts in hold_best.

Now let’s see the difference with optimized wire resistance.

Figure2: Optimized wire resistance

In Figure 2 after optimizing wire resistance, the total stage delay reduced to 160ps in hold_best and 170ps in hold_worst. Skew between two corners in this case is only 10ps.

It is clear from the Figure 2 that, how large wire resistance can impact overall stage delay and create delay difference between two corners. Optimizing wire resistance will help to achieve better skew and timing across all corners also it will reduce the inconsistency in timing between corners.

Steps to reduce wire resistance during design implementation.

The effect of high resistance should mitigate through the physical design implementation flow. Current physical implementation tool support resistance aware timing optimization which also optimizes overall resistance during various stage of physical implementation. Following steps canbe followedduring each stage of design implementation.

1) Synthesis stage

For advance technology nodes, placement aware synthesis is very essential. Current synthesis tools has visibility of the exact location of standard cells and other logic, allowing more accurate estimation of wire delay resulting more convergent path to timing closure.

2) Placement stage

Constraints of maximum net length should be applied during placement to not allow tool to exceed the net length above certain limit. Also exploring alternative placement to shorten critical nets in the design helps to reduce the overall resistance in the design.

3) Global routing stage

Global routing plays very vital role in performing wire optimization. Global routing should not just count the routing tracks across the chip that meets the spacing requirement; it should be also timing and SI (Signal Integrity) driven. Today’s EDA tools should support global routing which can also consider the effect wire spreading, wire widening and shielding.

4) CTS stage

During CTS optimization if more routing resources allowed, then special metal layer should be used whose routing resistance is lower. Obviously SI aware clock tree is must in advance node like shielding and applying NDRs (non-default rules).

5) Detail routing stage

SI effect becomes more critical in high resistance design due to worse transition. Crosstalk optimization should be done during routing to minimize the crosstalk effect.

6) DFM stage

Routing optimization should be done to improve the yield and minimize wire and via count. Current tool provides this optimization which picks the nets to optimize based on their routing patterns and optimize via.

7) Increasing sign-off corner in layout tool

With the advance technology process characteristic, optimizing design in one corner is not sufficient. Number of sign-off corners has increased in advance technologies as compared to conventional technology. Most of the layout tool now supports the MMMC (Multi mode multi corner) feature. Furthermore, there was a limit of only one corner considered for clock generation. For this reason, a clock skew occurred at an unconsidered corner and hindered convergence of layout design in some cases. Now EDA tools support MMMC clock tree synthesis. Giving multiple corners during CTS will reduce the problem of clock skew at unconsidered corner.

Conclusion

With manufacturing process evolutions it becomes important for the semiconductor industry to critically address the issue that the new age has brought with itself. High speed and low power are not the only targets that designers have to design for. With 28nm node and below interconnect delay is becoming more dominant than cell delay and its impactshould be alleviatingin our physical implementation flow to get better design performance.

References

[1] “Timing optimization for resistance” by TSMC

[2] tsmc.com

 

Hardik Desai is Technical Lead in Physical Design at einfochips. Hardik has over 7 years of experience EDA industries and performed multiple designs to silicon. He has hands on experience in physical design cycle with latest tools and technologies.