Hardware-assisted verification gate counts soar

Hardware-assisted verification gate counts soar
By Richard Goering, EE Times
June 7, 2002 (3:31 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020607S0063

NEW ORLEANS — Hardware-assisted verification will reach new horizons at this year's Design Automation Conference, as both Cadence Design Systems' Quickturn division and Tharas Systems roll out products that are said to accommodate 128 million gates. Other vendors claiming gains in hardware-assisted verification include Alatek, Aldec and Axis Systems.

Quickturn has expanded its Palladium design verification system to support up to 128 million ASIC gates, as well as 64 Mbytes of memory and more than 8,000 physical I/Os for target system interfacing. A high-speed channel between the workstation and Palladium lowers interprocess latency and increases performance.

Software enhancements are said to provide tighter integration with Cadence's NC-Sim simulator and with testbench automation tools. A new standardized intellectual-property (IP) form factor lets users plug physical cores into Palladium. Turnkey b oards with cores from ARM and TriMedia technologies will be provided.

The new configurations will be available for purchase or for remote access (through Quickturn's QuickCycles Extended Access program) in the third quarter. The latter program costs roughly $15,000 to $18,000 per million gates per month.

Tharas Systems Inc., for its part, will announce a follow-on to the the 32 million RTL-gate-equivalent accelerator, the Hammer 32M, which rolled last month. Tharas now has a 128 million-gate solution that comprises four Hammer 32M boxes and distributed, parallel simulation technology from Avery Design Systems.

The Hammer 128MC, a four-cluster configuration, includes 16 Gbytes of memory and is priced at just under $2 million. The company claims the configuration provides a threefold performance boost and a fourfold compilation time improvement over a single Hammer 32M box. A single box already compiles 10 million RTL-gate equivalents in an hour, the company said.

Quickturn and Tharas compete with Axis Systems Inc., which in May announced Xtreme-II, claiming a 100 million-gate capacity for emulation, acceleration and simulation. The system enables platform verification, in which all levels of abstraction can be handled simultaneously.

Alatek Inc. is heading to New Orleans with Comulator N2.1, said to be the first verification system that offers acceleration, emulation and co-verification without requiring a separate chassis. The system plugs into a Sun workstation and supports up to 12.8 million gates.

Alatek is a spin-off of Aldec Inc., which resells Alatek hardware under the Riviera IPT label. Aldec has separately expanded Riviera IPT — which offers acceleration along with Aldec software — to 12 million FPGA gates.

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