Challenges associated with Digital-Analog combined IP's

Arun Kumar Barman , Tejbal Prasad & Sachin Jain
EDN (March 12, 2014)

More and more applications today rely on capturing and processing real time data, be it in the form of stream of audio, video or radio data or real time data coming from various sensors such as temperature, pressure and safety monitors, etc. This is leading to an increase in the number of Analog IP content in the device. Most of these Analog IP’s have a Digital controlling logic associated with them that allows for the configuration of these Analog blocks for required configurations as well as facilitating the transfer of captured data to and from the core within the chipset.

What is Mixed-Signal IP ?

An IP is called mixed-signal when it consists of both Analog circuits and Digital logic. The Analog circuit is delivered as a hard-macro in Graphic Data System (GDS) format and the digital logic is delivered as soft program at RTL level written in VHDL, Verilog or System-verilog. The combined part is delivered as a Digital-Analog (DA) block for integration at the System On chip (SoC) level.

Typically the Digital part of a Mixed Signal IP enables following functionality:

User configurability: It allows for configuring the programming Registers of the Mixed Signal IP. All the parameterization – both static and dynamic are handled by this block.

Communication with the Analog block: This part of the logic is more challenging. This logic controls and responds to the analog part of the IP. The Analog part could be as simple as just one simple analog comparator or a very complex one like multiple comparators, analog multiplexes or phase locked loops; however analog always works as per the configuration of the digital model. An example is a 2 input Analog Comparator logic where the inputs are provided by the digital interface which also controls the duration until these inputs are exposed on the analog interface. The digital logic also takes care of these timing aspects of these analog circuits.

With the increase in complexity and the content of these Analog blocks, there is an enhanced focus to move more and more functionality, wherever possible, into the Digital domain which allows faster modifications, easy reuse and portability across technology nodes. Having said that there are inherent challenges associated with such Digital-Analog combined IP’s, referred to as Mixed Signal IP’s hereafter, both in Design and Verification in order to robustly signoff such IP’s at block verification level for integration in any SoC.

This paper discusses in detail these challenges and details certain steps that should be followed for faster and robust verification signoff of such Mixed Signal IP’s.

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