English
NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
PCI Express vs. Ethernet: A showdown or coexistence?
Krishna Mallampati, PLX Technology
embedded.com (March 08, 2014)
Until now, the boundaries between PCI Express (PCIe) and Ethernet were clearly defined -- PCIe as a chip-to-chip interconnect, and Ethernet as a system-to-system technology. There are good reasons (and a few less good) why these two technologies have both endured and co-existed. While nothing is on the horizon that will change this, PCIe is showing signs of growing and competing with Ethernet for space that was once solely the domain of Ethernet – specifically, within the rack. Can it really compete with and win against Ethernet?
Current architecture
Traditional systems currently being deployed in volume have several interconnect technologies that need to be supported. As Figure 1 shows, Fibre Channel and Ethernet are two examples of these interconnects (obviously, there could be more -- for example, InfiniBand).
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Integrating a PCI Express Digital IP Core into a Gigabit Ethernet Controller
- PCI Express Design Considerations -- RapidChip Platform ASIC vs. FPGA Design Efficiency
- Ethernet, PCI Express ride interconnects
- PCIe 5.0 vs. Emerging Protocol Standards - Will PCIe 5.0 Become Ubiquitous in Tomorrow's SoCs?
- PCI Express 3.0 needs reliable timing design
New Articles
- Optimizing 16-Bit Unsigned Multipliers with Reversible Logic Gates for an Enhanced Performance
- How NoC architecture solves MCU design challenges
- Automating Hardware-Software Consistency in Complex SoCs
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers