Ajay Jayaraj, Texas Instruments
embedded.com (April 25, 2014)
Over the last decade, the market demand for increased processing performance with reduced power and area footprint has remained strong and embedded SoCs have stepped up to the challenge. This performance, power and area (PPA) improvement has been achieved by adding cores – both general purpose cores and specialized cores such as DSPs and GPUs among other things. This trend has resulted in networks of heterogeneous multicore embedded SoCs.
Traditional approaches to programming such complex SoCs focus on manually partitioning the application across the various cores and hand optimizing the appropriate sections of the application for a given core. This approach tends to yield the maximum entitlement but has the following drawbacks:
- The partitioning is static and has to be redone for each system configuration.
- Increased time to market because programmers need to develop their own dispatch, communication and synchronization mechanisms
- The resulting application is not portable
- Requires detailed knowledge of the SoC and network architecture
- Make modeling “what-if” scenarios difficult because significant rework is required to move a section of the application that has been mapped and optimized for one type core to another core
An important observation is that as embedded SoCs increase in complexity, they are starting to look a lot like their desktop counterparts from a software architecture standpoint.
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