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Optimizing embedded software for power efficiency: Part 2 - Minimizing hardware power
Rob Oshana, Freescale Semiconductor and Mark Kraeling, General Electric
embedded.com (May 11, 2014)
Data flow optimization focuses on working to minimize the power cost of utilizing different memories, buses, and peripherals where data can be stored or transmitted by taking advantage of relevant features and concepts. Algorithmic optimization refers to making changes in code to affect how the cores process data, such as how instructions or loops are handled.
Hardware optimization, as discussed here, focuses more on how to optimize clock control and power features provided in the microprocessor or peripheral circuits.
Low power modes. DSP applications normally work on tasks in packets, frames, or chunks. For example, in a media player, frames of video data may come in at 60 frames per second to be decoded, while the actual decoding work may take the processor orders of magnitude less than 1/60th of a second, giving us a chance to utilize sleep modes, shut down peripherals, and organize memory, all to reduce power consumption and maximize efficiency.
We must also keep in mind that the power-consumption profile varies based on application. For instance, two differing hand-held devices, an MP3 player and a cellular phone, will have two very different power profiles.
The cellular phone spends most of its time in an idle state, and when in a call is still not working at full capacity during the entire call duration as speech will commonly contain pauses which are long in terms of the processor’s clock cycles.
For both of these power profiles, software-enabled low-power modes (modes/features/ controls) are used to save power, and the question for the programmer is how to use them efficiently. A quick note to the reader: different device documents may refer to features discussed in this section such as gating and scaling in various ways, such as low-power modes, power saving modes, power controls, etc. The most common modes available consist of power gating, clock gating, voltage scaling, and clock scaling.
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