USB V3.1 Power Delivery Type-C Port Evaluation board for OTI9108 IP
Optimizing embedded software for power efficiency: Part 3 - Optimizing data flow and memory
Rob Oshana, Freescale Semiconductor and Mark Kraeling, General Electric
embedded.com (May 14, 2014)
Because clocks in an embedded system design have to be activated not only in the core components, but also in buses and memory cells, memory-related functionality can be quite power-hungry, but luckily memory access and data paths can also be optimized to reduce power.
This third in a series of articles covers methods to optimize power consumption with regard to access to DDR and SRAM memories by utilizing knowledge of the hardware design of these memory types. Then we will cover ways to take advantage of other specific memory set-ups at the SoC level.
Common practice is to optimize memory in order to maximize the locality of critical or heavily used data and code by placing as much in cache as possible. Cache misses incur not only core stall penalties, but also power penalties as more bus activity is needed, and higher-level memories (internal device SRAM, or external device DDR) are activated and consume power. As a rule, access to higher-level memory such as DDR is not as common as internal memory accesses, so high-level memory accesses are easier to plan, and thus optimize.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- Optimizing embedded software for power efficiency: Part 4 - Peripheral and algorithmic optimization
- Optimizing embedded software for power efficiency: Part 2 - Minimizing hardware power
- Optimizing embedded software for power efficiency: Part 1 - measuring power
- Dealing with automotive software complexity with virtual prototyping - Part 3: Embedded software testing
- Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II
New Articles
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
- Timing Optimization Technique Using Useful Skew in 5nm Technology Node
- Streamlining SoC Design with IDS-Integrate™
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- UPF Constraint coding for SoC - A Case Study