Optimizing embedded software for power efficiency: Part 4 - Peripheral and algorithmic optimization
Rob Oshana, Freescale Semiconductor and Mark Kraeling, General Electric
embedded.com (May 14, 2014)
When considering the impact of reading and writing of data has on an embedded system’s power utilization we cannot just think about memory access: we need to pull data into and out of the device as well. Here we will we will look at how to minimize power consumption in commonly used embedded processor (I/O) peripherals. Later we will talk about the various algorithmic techniques for power management.
On the first topic, things to consider include the peripheral’s burst size, speed grade, transfer width, and general communication modes. The main standard forms of peripheral communication for embedded processors include DMA (direct memory access), SRIO (serial rapid I/O), Ethernet, PCI Express, and RF antenna interfaces. I2C and UART are also commonly used, though mostly for initialization and debug purposes.
The fact that communication interfaces usually require their own PLLs/clocks increases the individual power consumption impact. The higher-clocked peripherals that we need to consider as the main power consumers are the DMA, SRIO, Ethernet, and PCI Express. Clock gating and peripheral low-power modes for these peripherals were discussed in the low-power modes section of this chapter, so this section will talk about how to optimize actual usage.
Although each protocol is different for the I/O peripherals and the internal DMA, they all share the fact that they are used to read/write data. As such, one basic goal is to maximize the throughput while the peripheral is active in order to maximize efficiency and the time the peripheral/device can be in a low-power state, thus minimizing the active clock times.
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