Building mesh-based distributed switch fabrics with programmable logic
By EE Times
July 1, 2002 (10:36 a.m. EST)
Charles Hill, System Architect, Motorola Computer Group, Schaumburg, IL , Martin S. Won, Senior Member, Technical Staff, Altera Corp., San Jose, Calif.
Mesh networks can be used to build distributed switch fabrics. Distributed fabrics contain multiple identical nodes each taking care of their own switching needs, thus eliminating the need for a centralized fabric. Essentially, distributed fabrics offer several benefits over centralized fabrics in performance, reliability, and scalability. For systems with mixed protocols, distributed fabrics offer advantages as well, including greater interoperability and better traffic management. Supporting multiple protocols such as Internet protocol (IP) and asynchronous transfer mode (ATM) simultaneously in a single platform can facilitate network evolution like the 2.5G to 3G evolution in wireless. Due to these advantages, distributed switch fabrics are a coming trend in equipment stand ards like PCI Industrial Computer Manufacturers Group (PICMG) 2.20 and PICMG 3.0 using high-speed serial mesh topologies.
The latest programmable logic devices (PLDs) are equipped with built-in transceivers, enabling them to act as the high-speed links from the line card functions to the backplane in these mesh networks. These PLDs can also perform traffic aggregation, flow control, and traffic management functions, as well as interface to network processors and other components on the line card. The flexibility of PLDs is particularly important in the latter function in that their design can be changed to meet the needs of evolving chip-to-chip interfaces such as the Network Processor Group's Common Switch Interface (CSIX), the Optical Internetworking Forum's System Packet Interface (SPI-4.2), HyperTransport, and RapidIO.
High-end, carrier grade switch fabrics found in much of today's telecom equipment are generally partitioned into multiple elements with a star topology. In star topologi es, each device uses a dedicated link to send/receive data from a centralized fabric. Reliance on a single central resource can cause a loss of all elements below the failure, so star topologies require redundancy to provide reliability. In mesh-based distributed switch fabrics, the mesh populates point-to-point connections until all nodes have connections to all other nodes. At this point, the hierarchy found in a star network disappears. Each node switches its own traffic, so each node can be an endpoint, a router, or both. There is no dependence on a central switching resource, no single point of failure, and therefore greater reliability than star networks.
In many current switch architectures, the "traffic managers" receive the layer-two traffic and classify and schedule it. The traffic managers encapsulate the layer-two traffic into a format specific to the lower layer fabric. In this way, t he fabric can transport a variety of different protocols by connecting traffic managers specialized for each protocol type. Most commercial off-the-shelf fabrics of this type have industry-standard interfaces to the traffic managers, but have proprietary interfaces and protocols between the traffic managers and the fabric. This creates a problem for open architecture systems with line cards from multiple vendors.
Mesh-based distributed switch fabrics provide greater interoperability by standardizing on high-speed serial backplanes consisting of 100-ohm differential transmit and receive pairs per channel. The interface between the line cards and the backplane can be handled via PLDs that incorporate high-speed transceivers that include clock-data recovery, serial/derserialization (SERDES) functions, and 8b/10b encoding. Currently available PLDs like Altera Mercury field-programmable gate arrays (FPGAs) offer this technology at relatively low cost (less than $6 per port), making a high number of co nnections in a mesh very cost effective.
Engineers in the Motorola Computer Group are developing the Multi-Service Packet Transform Platform or MXP based on the proposed CompactPCI Serial Mesh Backplane (CSMB) standard. The CSMB standard is a point-to-point serial interconnect that can achieve up to 700 Gbit/second throughput and is intended to enable telecom OEMs to build scalable, high-speed packet environments that can to connect ATM, IP, circuit-switched, and other networks. The MXP achieves this environment by offering up to 18 slots for line cards to handle general-purpose or protocol-specific tasks.
In the MXP architecture, these slots are fully connected via a mesh network, and Altera Mercury's FPGAs are used to interface to the backplane. Mercury FPGAs are ideal for this function because they offer up to 18 CDR channels, and are able to provide an independent channel for each line card connected to the backplane.
In add ition to interfacing to the backplane, the Mercury FPGAs perform traffic aggregation and flow control. In this way, the PLDs, in conjunction with the blackplane, act as the switch fabric. Programmable logic is valuable in this role because it can also handle the interfaces to the network processor or other processing device that performs the main traffic management functions. These interfaces, such as CSIX, Hyperstransport, RapidIO, and SPI-4.2 are currently evolving, and require the kind of flexibility in implementation that programmable logic can provide.
The MXP platform can accept third-party line card that are built to meet the CSMB standard. In these cards, PLDs like Mercury FPGAs can perform switch fabric operations as well. In addition, the developer can take advantage of the PLD for other functions. For example, the PLD can implement custom traffic shaping algorithms, extra error detection, or accommodations for additional services. The developer can also redirect aspects of traffic m anagement away from the network processor to the PLD to achieve hardware acceleration for mission-critical functions, or to increase datapath bandwidth. In some cases, such as when handling ATM traffic, a network processor might not be needed, and operations like segmentation and reassembly and header/payload processing could be handled by PLDs instead. By customizing the PLD design in this way, the developer can include specific value-added features in their product.
Bandwidth requirements, cost and scalability considerations make mesh-based distributed switch fabrics an ideal choice for the coming generation of carrier-class telecom equipment. PLDs that include built-in transceiver functionality like Mercury FPGAs can implement critical portions of the systems utilizing these fabrics, including backplane interface, traffic aggregation, flow control and traffic management. In addition, programmable logic offers the flexibility to change with the evolving chip-to-chip standards that are prevalent in this design space. Most importantly, PLDs enable designers to quickly realize, evaluate, and refine their value-added proposition for these products, which will underpin the next-generation communications infrastructure.