FPGAs: Embedded Apps : OC-48 SONET receiver consumes significantly less logic in FPGA

In many Sonet processing applications, a commercial vendor application-specific IC (ASIC) or application-specific standard product (ASSP) implements basic Sonet functions such as framing and performance monitoring. Frequently, a field-programmable gate array (FPGA) is also required to interface to the ASIC and perform customer-specific functions. Traditionally, the ASIC/ASSP plus FPGA solution has been less expensive than incorporating the Sonet functions directly into the FPGA. The size of the Synchronous Optical Network (Sonet) cores in FPGAs means the FPGA solution is frequently more expensive than using the commercial ASIC/ASSP for the Sonet processing.

For example, one commercially available OC-3c FPGA core requires almost 90 percent of a 200,000-gate device. If the FPGA costs $250, then the core consumes over $210 of the part, leaving almost no usable area for ad ditional customer logic. This doesn't include the amortized cost of the core, or the additional cost of a configuration device if one is used. Compared to commercial performance monitoring chips that cost around $170, this is not a bargain. Additionally, many commercial ASIC/ASSP vendors put as much functionality into one chip as possible. This makes good business sense for the chip vendor, as one device can appeal to a broader customer base.

However, many customers only need a subset of the available functions, yet have to pay for all the logic in the device even though some of it never gets used in their application. "Payment," in this context, may take the form of dollars, power consumption, increased circuit real estate, or increased system complexity that can reduce system reliability. An FPGA-based approach would allow the customer to instantiate only the functions desired, and could significantly reduce the cost and size of implementing those functions.

For an FPGA-based Sonet design to be competitive, it has to be quite small so that it consumes only a small percentage of a target FPGA. Our goal was to create an OC-48 design that consumed less than $50 worth of a 200,000-gate FPGA, leaving most of the logic for customer use.

Very early in the process it was determined that using HDL design methods could not meet this ambitious goal in a reasonable time frame. A more traditional gate-level design approach was required to squeeze maximum performance out of the minimum number of gates, and to get it done quickly. Designing efficiently in programmable logic requires the designer, by necessity, to "think small" from the beginning of the design phase. Resources are limited and positioned in fixed locations. Working within the constraints of the FPGA architecture can mean the difference between a lean design and an overly bloated one. The inherent abstraction of HDL methods tends to create solut ions that fall in the latter category.

Real-time tests

It was also decided that a hardware platform for testing the cores was required to speed overall development. Simulations are useful to a point, but a faster and more comprehensive test is to program a device and verify the design using standard Sonet test equipment. Since ANSI, Telcordia, and ITU-T telecom standards were not created with computer simulations in mind, full-frame simulations tend to be exceedingly large. One second of real-time testing can tell you more than hours, days or sometimes weeks of simulation time. This is most apparent when testing pointer processing, with 783 pointer possibilities that must be tested against increments, decrements, mismatches and NDF events, all while following the "eight-out-of-ten" pointer bit match rules. The hardware platform would also allow customers to verify full operation of the core for themselves prior to purchase, significantly reducing their risk and uncert ainty in using purchased intellectual property.

The first cut of the OC-48 receiver design was completed in under eight weeks, and included frame synchronization, descrambling, B1 and B2 calculation and error accumulation, concatenated pointer processing, B3 calculation and error accumulation, and payload extraction. With all pieces included, this design used about 20 percent of a 200,000-gate device. After the circuit board arrived, design testing began. During this process, some major design simplifications were made, resulting in a further 40 percent reduction in the core size. With pointer processing included, the core now requires about 12 percent of a 200,000-gate device. With pointer processing functions removed to more closely match the functionality of commercially available OC-48 performance monitors, the core requires about 9 percent of the device.

In a $250 200,000-gate device, one Core Foundry OC-48c receiver core uses about $30 worth of logic. This is well below the $50 target, and 88 percent of the logic is available for the customer. In less expensive, smaller devices, this cost can be reduced further, to under $15 per port. If the pointer processing is removed, and only B1/B2 functionality is used, the cost drops below $10 for basic OC-48 performance monitoring. This compares quite favorably to the $170 commercial ASIC/ASSP, and to the aforementioned OC-3c core that was over 7 times larger, while processing data that is 16 times slower.

FPGAs offer several significant advantages over commercially available ASICs/ASSPs. Multiple port instantiations may be designed into a single device, leaving substantial room for follow-on packet or payload processing. Engineers have the opportunity to test their designs against real-world conditions before committing the design to a specific vendor's part. Emerging standards and proprietary formats are readily supported without waiting for ASIC vendors to make a commitment. Instantiating the cores in an FPGA would also significantly red uce time-to-market and eliminate the prohibitively expensive NRE costs associated with custom ASIC development.