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variable vector size

sc_int<width>, sc_uint<width>, sc_bigint<width>

They can have different sizes

Varable vector size
sc_lv<width>

e.g.

sc_signal <sc_logic>abc

sc_logic is the template argument. This template can be any of systemC data types

e.g.

Wire abc is same as wire logic abc in system verilog

var i is same as

var logic i

All variable within automatic tasks and automatic functions are automatic

1. Enum{flag[2:0], host[2]}

is same as enum{flag2, flag1, flag0, host0, host1, host2}

2. enum {flag[5]} is same as enum {flag0, flag1, flag2, flag3, flag4}

3. literals can be other data types

enum bit[2:0]{a, b, c, d}

4. you can assign x and Z value to literals, if it is a 4 state type

e.g :

enum logic[2:0] {a, b=11x, c=001}xyz

4. Built in methods are available

a. variable structure

b. wire structure

e.g for wire structure

Typedef struct

{

logic clk;

logic [31:0] address;

}ctrl

wire ctrl signals;

Typedef struct{

logic [3:0] a = 'b1011;

bit [2:0]b ='b110;

}bit_var;

Vector access

struct tag {

sc_bv<8> var;

sc_bv<8>var2;

}obj;

obj.var.range(5, 0) = 4

Struct packed

{

short int shr;

int adr;

short int dhr;

}test1;

test1[15:0] coressponds to shr.

system verilog

test1[16:0] = 17'h10001

would result in adr =1 and dhr =1

but in systemC you cannot access var and var2 simultaneously using vector

Structure memory
struct abc

{

short int a;

short int b;

int c;

}xyz;

STL(Standard Template Library)

or

bit[3:0]ctr[20]

Available

Same as C++ .

STL(Standard Template Library)

They refer it as list and it as standard keyword

member functions

Class Property
Class method

1. Global constant

2. instance constant

Const int j =20;

//instance constant

const int j;

// j can be assigned later(run time)

{

sc_in <bool/int/sc_logic>a,

sc_out <bool/int/sc_logic>b;

};

or

Module abc(input a, output reg b)

In system verilog class and Modules are different but in systemC SC_MODULE will be treated as class internally. SC_MODULE is a macro which replaces class abc: public sc_module. sc_module is a predefined class

In system verilog it is outside always block

Available

it has built in methods

In system verilog event hastriggered property and assigning of events is possible.

SystemC does not have triggered property and assigning of events is not possible

1. if

2. unique if

3. unique0 if

4. priority if

2. unique case

3. unique0 case

4. priority case

Interface functionality is same in both but syntax is different