English
OTP/eMTP: 8K - 512Kbit NVM in 110nm Standard Logic CMOS process
Challenges in LBIST validation for high reliability SoCs
Abhinav Gaur & Gaurav Jain (Freescale)
EDN -- July 19, 2014
Logic built-in self test (LBIST) is being used in SoCs for increasing safety and to provide a self-testing capability. LBIST design works on the principle of STUMPS architecture. STUMPS is a nested acronym, standing for Self-Test Using MISR (Multiple Input Signature Register) and Parallel SRSG (Shift Register Sequence Generator). It consists of a Pseudo Random pattern generator (PRPG) for generating the test stimuli for the scan input, and Multiple Input Signature Register (or MISR) for collecting the scan output. If the final MISR signature matches with the golden or expected MISR signature, the LBIST status is “Pass”.
For any SoC that provides the LBIST functionality, there will be a need for tester patterns for production, for checking whether the LBIST is working properly on each of the samples being delivered to the customer. This paper will discuss the various challenges while developing these LBIST tester patterns for production, and ways of creating such patterns efficiently.
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