by Jon Turino
Fundamental changes in the SoC design and test arenas are beginning to accelerate as chip design methodologies migrate towards the reusable IP model and the devices become ever more complex. Some leading edge companies such as IBM, Motorola, LSI Logic and others have anticipated the testing challenges associated with multi-million gate deep sub-micron ICs and have incorporated DFT and BIST techniques for several years.
Almost every IDM, fabless design house and foundry now accepts IEEE-Std-1149.1 (JTAG) boundary scan as a given, and the use of the test access port has been expanded for on-chip debugging, in-system programming, control of internal scan chains and activation of BIST circuitry. A search on the topic of built-in self-test on the Internet yields almost 10,000 hits. But market researchers peg the BIST market -- for both IP and the tools to implement it -- at well under $100 million.
The third party functional IP market -- processors, DSPs, etc. -- in contrast, is expected to reach $3 billion by 2005. A March 2000, survey of a dozen or so IP vendors at DesignCon in Santa Clara, Calif., revealed that only two of the twelve even knew what the acronym BIST stood for. So it seems that there is still a significant disconnect between the companies that want to use BIST and the people who must supply it to the circuit designers.