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AES (ECB), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores
MBIST verification: Best practices & challenges
Abhilash Kaushal & Kartik Kathuria (Freescale)
EDN (July 25, 2014)
Embedded memories are an indispensable part of any deep submicron System on a Chip (SoC). The requirement arises not only to validate the digital logic against manufacturing defects but also do robust testing of large memory blocks post-manufacturing. MBIST (Memory built-in self-test) provides an effective solution for testing of such large memories. Verification of functioning MBIST is an essential part in any SoC design cycle, as it enables the designer to detect beforehand any issues related to MBIST. The main focus of this paper is to discuss the general issues faced, and best practices to be followed, during MBIST Verification.
MBIST is a self test logic that generates effective set of March Algorithms through inbuilt clock, data and address generator and read/write controller to detect possibly all faults that could be present inside a typical RAM cell whether it is stuck at 0/1 or slow to rise, slow to fall transition faults or coupling faults.
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