Jonathan Harris, product applications engineer, Analog Devices, High-speed converter group
EDN (September 24, 2014)
As high speed analog-to-digital converters (ADCs) move into the gigasample-per-second (GSPS) range, the interface of choice for data transfer to FPGAs (or custom ASICs) employs the JESD204B protocol. In order to capture RF spectrum higher in the frequency range, wideband RF ADCs are necessary. With this push to GSPS ADCs that capture wider bandwidths and allow for more configurable SDR (software defined radio) platforms, a high speed serial interface, JESD204B in this case, is necessary. It is important to understand that the JESD204B standard is a layered specification.
Each layer within the specification has its own function to perform. The application layer allows for configuration and data mapping of the JESD204B link. The transport layer maps conversion samples to and from framed non-scrambled octets. The scrambling layers can optionally take those octets and scramble or descramble them in order to reduce EMI effects by spreading the spectral peaks. Scrambling would be done in the transmitter and descrambling done in the receiver. The data link layer is where the optionally scrambled octets are encoded to 10-bit characters. This layer is also where control character generation or detection is done for lane alignment monitoring and maintenance. The physical layer is the serializer/deserializer or (SERDES) layer responsible for transmitting or receiving the characters at line rate speeds. This layer includes the serializer, the drivers, the receivers, the clock and data recovery, etc. The figure 1 shows the arrangement of these layers within the JESD204B specification. To better understand the specification a closer examination of each layer is beneficial so that it can be seen how the ADC samples are mapped to 8b/10b serialized words.
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