Targeting SoC address decoder faults using functional patterns

Aashish Mittal, Glenn Carson, and Nitin Goel, Freescale Semiconductor
embedded.com (September 28, 2014)

Even though you have thoroughly verified your SoC design during the development cycle, sometimes critical faults during manufacturing can lead to failure in the field, one of the most serious of which is the address decoder stuck-at fault [1]. This is a critical fault that must be tested for on each and every piece of silicon that needs to pass qualification for an industry standard [2].

Testing of RAM and other memories come under the scope of Design for Test (DFT). It is generally achieved by implementing a number of algorithms which are either part of MBIST (memory built-in self test) delivered by a third party or DFT patterns targeted for particular faults in memory [3]. Conventionally, no special fault detection technique is used for an address decoder as they are assumed to be covered with array testing. Some of earlier MBIST controllers do not support Algos for checking ASOF faults, so our approach is to use a functional tester pattern to catch these faults on silicon.

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