Jonathan Harris, Analog Devices
EDN (September 24, 2014)
Data Link Layer
The data link layer takes in the parallel framed data (containing ADC samples, control bits, and tail bits) and outputs 8b/10b words that are serialized in the physical layer and can optionally be scrambled. The 8b/10b scheme adds some overhead but provides DC balanced output data and built-in error checking. The data link layer synchronizes the JESD204B link through the link establishment process. The link establishment consists of three distinct phases: 1 – Code Group Synchronization (CGS), 2 – Initial Lane Alignment Sequence (ILAS), and 3 – User Data.
During the Code Group Synchronization (CGS), each receiver (FPGA) must locate K28.5 characters in its input data stream that is being transmitted from the ADC using Clock and Data Recovery (CDR) techniques. Once a certain number of consecutive K28.5 characters have been detected on all link lanes, the receiver block de-asserts the SYNC~ signal to the transmitter block. In JESD204A, the transmit block captures the change in SYNC~ and after a fixed number of frame clocks, starts the ILAS. In JESD204B, the transmit block captures the change in SYNC~ and starts the ILAS on the next local multiframe clock (LMFC) boundary.
In the ILAS, the main purpose is to align all the lanes of the link, to verify the parameters of the link, and to establish where the frame and multiframe boundaries are in the incoming data stream at the receiver. During ILAS, the link parameters are sent to the receiver (FPGA) to designate how data will be sent to the receiver. The ILAS consists of 4 or more multi-frames. The last character or each multi-frame is a multi-frame alignment character /A/. The first, third, and fourth multi-frames begin with an /R/ character and ends with an /A/ character. For the case of ADI ADCs, the data in between them is ramp data. The receiver uses the final /A/ of each lane to align the ends of the multi-frames within the receiver.
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