Multiple clock domain SoCs: Verification techniques
Tejas Dave, Amit Jain & Divyanshu Jain (eInfochips)
EDN (October 23, 2014)
With technology advancement and introduction of more complex SOCs, data transfer between multiple clock domains is more frequent and demanding, and CDC design and verification becomes a more challenging task. An understanding of metastability plays a key role in understanding CDC problems and associated design challenges. Adoption of new verification techniques in the early stages also plays an important role in easing and speeding up multi-clock domain design and verification activities.
EDA tool vendors provide various solutions to check whether proper implementation of CDC is done or not. EDA vendors like Synopsys, Atrenta, Mentor, and Cadence provide solutions through simulation, Linting, and LEC. Here are some of our experiences:
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- Optimizing clock tree distribution in SoCs with multiple clock sinks
- The Challenge of the Clock Domain Crossing verification in DO-254
- Clock Domain Crossing Glitch Detection Using Formal Verification
- Verifying Dynamic Clock switching in Power-Critical SoCs
- Integrated ADAS Domain Controller SoCs with ISO 26262 Certified IP
New Articles
- Safeguarding the Arm Ecosystem with PSA Certified PUF-based Crypto Coprocessor
- Mastering Key Technologies to Realize the Dream - M31 IP Integration Services
- Create high-performance SoCs using network-on-chip IP
- IoT Security: Exploring Risks and Countermeasures Across Industries
- How Efinix is Conquering the Hurdle of Hardware Acceleration for Devices at the Edge