English
MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
IC mixed-mode verification: The Sandwiched-SPICE approach
Garima Jain (Freescale)
EDN -- October 21, 2014
RTL- and SPICE-based mixed-signal verification means picking SPICE view for a number of modules (those involved in the concerned test case), and behavioral models for the remaining modules. As analog front-end modules get more complex, AMS verification has become even more challenging.
The limitations to be considered are as follows:
- The number of transistors the module taken in SPICE can have, or,
- The number of fast toggling signals (high frequency clocks etc.) which can be in the module to have reasonable run time.
The case may be such that the number of transistors is acceptable and there are just a couple of fast toggling signals. But what if this is not so? What if the number of fast toggling signals is large, or the netlist size of the module whose SPICE view is being picked is large, or both?
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