Adnan Hamid (Breker Verification Systems), Bill Neifert (Carbon Design Systems)
EETimes) 12/3/2014 06:30 PM EST
The evolution from chip to system-on-chip (SoC) has brought value to both the engineering community and end users. With the move to greater complexity, problems that were once isolated to individual design blocks are now system-level concerns. Cache coherency is just the latest of these concerns. Every SoC team is facing or will face this challenge. Cache coherency interacts with many aspects of SoC functionality. Proper verification requires fast cycle-accurate models and coherency-aware randomized stress test cases.
The reason for this major change is the rapid evolution of chip design and verification. Most large, complex chips now contain at least one embedded processor and qualify as SoC designs. Most SoCs contain multiple processors (possibly heterogeneous), and most multiprocessor designs now include caches to reduce memory latency and maximize system bandwidth. Further, in the latest generation of SoCs, designers are adding cache-coherent agents beyond the multiprocessor clusters.
Cache coherency, long regarded as one of the most complex verification challenges, is no longer an issue for CPU developers only. This article presents a highly automated approach to cache coherency verification at the SoC level: generation of test cases to stress every aspect of a multiprocessor, multi-memory, multi-level cache design. This solution requires no specialized knowledge of cache algorithms or of the underlying generation technology.
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