Max Maxfield, Designline Editor
EETimes (12/17/2014 04:05 PM EST)
The JESD204 serial interface standard -- the latest version of which is the JESD204B revision -- was created under the auspices of the JEDEC committee to standardize and reduce the number of data inputs/outputs between high-speed data converters, such as analog-to-digital converters and digital-to-analog converters, and other devices, such as SoCs and FPGAs.
High-speed serial interfaces like JESD204B have several advantages over their traditional parallel counterparts. In addition to minimizing the I/O pins used in chip-to-chip communication, for example, they ease routing congestion at the board level.
One downside of the JESD204B standard is the fact that it uses 8b/10b encoding, in which each eight-bit data byte is converted into a 10-bit character/symbol for transmission to achieve DC balance and provide sufficient state changes to allow clock recovery. (The clock is embedded in the signal.) This extra pair of bits-per-byte results in a 25% overhead for each character; to put this another way, 20% of the channel is consumed by the 8b/10b encoding overhead.
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