A High Density, High Performance, Low Power Level Shifter
Gaurav Goyal (Freescale Semiconductor India Pvt. Ltd.)
These days, there is a requirement of achieving high frequency targets with lower power consumption. Achieving both the targets simultaneously is very difficult and the situation becomes even more complex while moving down the technology nodes due to various sub-micron effects. With more features being integrated in modern SoC’s, the total number of gates used is increasing. Moreover higher throughput necessitates operating the design at higher frequencies. All this leads to significant increases in power consumption and die size. The proposed circuit is a single supply level shifter to translate the signal from one power domain to another power domain.
Multiple techniques like several voltage domains are being created in order to cater for the need of low power requirements and to communicate between these two domains level shifters are being used. However, these techniques are not fully effective because part of the power saved by voltage islands is lost due to power consumed by energy eating inefficient level shifter cells. It has been observed that the usage of level shifters is increasing day by day so it is absolutely necessary to have high performance and high density with least power consuming level shifter solution. Below is a conventional single supply level shifter architecture widely used.
Fig 1 Conventional Single supply level shifter circuit.
Generally, any double supply architecture has two different wells for both corresponding supplies which results in physically isolated wells at the layout and those results in much greater usage of area. It is not required for the architectures which are based on single supply topology (Single height layout). So, there is a saving in terms of area and routing resources and less complexity for single supply architectures as compared to the double supply architectures.
Any level shifter design is limited by the range of input-output voltage range supplies it supports. The majority of the level shifter designs are capable of translating signals between those voltage domains where the difference in the voltages is less than or equal to threshold voltage (Vt) of the transistor i.e. vddo – vddi <= Vt. They are bound to dissipate a huge amount of power once the difference in the voltage domains gets larger than the Vt of the transistor i.e. vddo – vddi >= Vt,
vddo = output voltage domain voltage
vddi = input voltage domain voltage;
So, there is a need to have a solution which has the ability to translate the signals from any voltage domain to any voltage domain with minimal power dissipation and is also a high density solution with comparable timing parameters.
Below is a level shifter circuit, which caters to the need of voltage signals translation when vddo – vddi >= Vt & vddo –vddi <= Vt i.e. in both cases.
Proposed Circuit : Operation of the proposed circuit when input ‘A’ is at ‘vddi’ V.
Fig 2. Proposed circuit for single supply level shifter architecture working when input ‘A’ is at vddi voltage.
Below is the working of the proposed circuit when input ‘A’ is at ‘0’ V.
Fig 3. Proposed circuit for single supply level shifter architecture working when input ‘A’ is at gnd voltage.
Fig. 4 is the simulation waveforms for the proposed circuit depicting input ‘A’ & output ‘Z’ with an internal node ‘b’.
Fig 4. Proposed circuit for single supply level shifter architecture simulation waveforms.
The proposed circuit was simulated under following conditions and compared with the conventional circuit for performance numbers when traversing from vddi to vddo:
For much less voltage translation i.e. when vddo – vddi <= Vt
Table 1. Analysis for conventional and proposed circuits vddo – vddi <= Vt.
For much wider voltage translation i.e. when vddo – vddi > = Vt
Table 2. Analysis for conventional and proposed circuits for vddo – vddi >= Vt.
Table 3. Analysis of different parameters for conventional and proposed circuits.
The Proposed circuit has the distinguished ability to translate the signals for very wide range of voltage translations without any loss in performance parameters.
1. A New Level Shifter with Low Power in Multi-Voltage System By: Bo Zhang, Liping Liang, Xingjun Wang, Research Institute of Information Technology of Tsinghua University, Beijing 100084, China,
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