VSIA guidelines assist SoC Signal Integrity
VSIA guidelines assist SoC Signal Integrity
By Raminderpal Singh, Senior engineer, IBM Communications Research and Development Center, Essex Junction, Vt., EEdesign
February 28, 2003 (4:55 p.m. EST)
Authors and integrators of intellectual property (IP) are trying to tape out chips without real verification of chip-level signal integrity matters. EDA solutions are complex and inadequate, with capacity-limited extraction tools that run out of steam well before system-on-chip (SoC) design sizes are met. The Virtual Socket Interface Alliance (VSIA) has taken a pragmatic approach to building an infrastructure of important concerns interconnect crosstalk, inductance, power grid noise, substrate noise and developing useful guidelines for SoC IP authors and integrators.
Digital or mixed-signal SoC designs today are typically large, with some limited analog and RF content. Designers are coping with crosstalk, signal electro-migration, supply and ground electro-migration and substrate coupling. These problems are not limited to analog-type circuitry. In fact, in high-gate-count, digital-only designs, power grid problems can occur at rel atively low frequencies (100 MHz to 200 MHz). The power grid drops lead to gate delay changes, which leads to timing issues. The end effect is a series of timing errors, with no real indication of why, when or how. If analog IP circuitry is included in the picture, then the signal integrity problems increase significantly.
Digital switching may lead to ground bounce, which could lead to substrate voltage bounce. These effects can easily find their way through backdoor routes, such as common connections between analog and digital grounds at the bond pads and even on the printed-circuit board. The frequencies of the signals must be carefully understood and analyzed. For example, noise spikes, from digital switching and capacitive coupling, can cause a broad spectrum of noise or simply be at a frequency too high to couple to the analog signal. In any case, as 0.1 micron and below approaches and the opportunities for highly integrated fast-switching designs become prevalent, the noise problems will only get worse. Somebody has to address this.
The EDA industry's answer is to provide a suite of disconnected tools, primarily introduced very late in the physical design flow, to "accurately analyze and fix" each and every problem. Users are offered numerous interconnect extraction tools, a series of supply and ground analysis tools and a couple of substrate extraction tools. Significantly, these disparate tools do not tie together, for example, to form a unified RLC model addressing the IC parasitic problem. Therefore, we currently have no complete solution to evaluate signal integrity concerns in SoC designs. This is a major problem.
But one should not lay the blame entirely with EDA tool suppliers. A lot of work has gone to improve the tools and flows, and generally the cost-to-return ratio of parasitic tool and flow development is unevenly high compared to other tools in the flow. However, as fast as new tool capabilities are emerging such as crosstalk checking and power grid macros f or chip-level checking the design noise problems are growing even faster. Add analog and the complexities of chip-level sign-off soon spin out of control. However, there may be another approach to solving this problem that industry should think about, a solution that can help lower the requirement burden on the EDA tools.
The VSIA approach
VSIA began its investigation into signal integrity early in 2000. Two years later, the first specifications document was released to members and more are on their way. Now, the signal integrity work is a major part of the hardware-related specifications development effort at VSIA. The key to that work has been to rethink the requirements for SoC success. VSIA's view of solving the signal integrity problem is to enforce a strict IP authoring, and then IP integration, methodology, similar, but more formal, than typical IC block-based design. SoC designs are premised on the integration of IP blocks, probably from different internal or external design groups to the integration design team. Thus, a definitive hand-off process has to occur and this can be used to an advantage.
In practice, many SoC design teams face schedule slippage because of incomplete or badly documented IP transfer. This can be very costly and not always due to technical problems. However, by taking a top-down view of the problem, executives can use the VSIA approach (or a derivative of it) to drive a consistent predictable schedule for the most complex SoC designs. Design teams can be organized to provide and receive IPs within a formal, efficient process. The same process can be used to pass and receive IP from third-party design teams, a very big advantage in today's business environment where fabless IP providers are more and more common.
VSIA's approach is split the problem into two levels of hierarchy, those associated solely with the IP blo ck, and those associated between the chip-level circuitry and the IP block, with the effects being in either direction.
VSIA assumes that hard IP blocks (black boxes) are provided and the specification development work helps IP authors characterize and package IP adequately for integration. Also, VSIA carefully organized the development efforts, so that the analog mixed-signal (AMS), implementation-verification (I-V) and signal integrity (SI) documents are aligned for the user.
The signal integrity specifications overlap into design scopes covered by the I-V and AMS specifications. Therefore, it is important that the reader understands the emphasis and focus of this document and how to apply the specifications from each area effectively. The most fundamental point is that the I-V and AMS documents cover the broad requirements for designing and integrating digital and analog IP blocks. The SI work overlays important and many times critical requirements above the requirements described in the A MS and I-V specification documents, borrowing many of the formats from them. This document uses different attributes of the formats to specify SI-related deliverables. For example, SDF, SPEF, Hspice and GDSII are all commonly referred to in the three documents. This allows the reader to accomplish compliance with the use of standard formats.
VSIA's approach provides the best methodologies for design teams to follow. The key is to marry the strength of this work to the EDA tools and formats to get the best of all worlds. Without good tools, no methodology can be implemented successfully. The methodology efforts of VSIA and the tools skills of the EDA industry have to be aligned to provide optimum solutions.
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