Darren Hobbs, S3 Group
Consumer’s voracious appetite for quick access mobile content is obligating the need for high-resolution, high-speed data convertors in their mobile internet devices. Whether the transmission pipe is via cellular networks such as LTE or via local networks such as WiFi, the end requirement for the data convertor remains largely the same, those being higher bandwidth, higher speed, lower power and ownership costs that the consumer market can tolerate. This paper presents the key emerging market requirements for high-speed data-convertors, the metrics to use, and the architectural choices. It completes with a review of a highly efficient SAR ADC.
Choosing the Best High-Speed ADC for Your SoC
Consumer’s voracious appetite for quick access mobile content is obligating the need for high-resolution, high-speed data convertors in their mobile internet devices. Whether the transmission pipe is via cellular networks such as LTE or via local networks such as WiFi, the end requirement for the data convertor remains largely the same, those being higher bandwidth, higher speed, lower power and ownership costs that the consumer market can tolerate.
Key Consumer Market Requirements
The three key drivers that are pushing the evolution of data convertor design are dynamic linearity over certain bandwidths, power consumption and silicon area. Presently, excellent dynamic linearity equivalent to greater than 10.2 ENOB is expected over bandwidths ranging from a few MHz to 80MHz, cellular LTE occupying the lower end, whilst WiFi’s 802.11ac occupies the higher-end. Typical power consumption budgets of less than 15mW are required, whilst silicon area utilization of the order of 0.15mm2 and below is permitted. These are certainly tough requirements and only getting tougher!
What Metrics TO USE
A good figure of merit for comparing the relative performance of data convertors is the energy efficiency metric. This is given simply as:
with Power expressed in mW and Fs representing the sampling rate in Ms/s. In essence this figure of merit captures the energy required per converted bit. The lower the number the better the relative performance. This metric, together with the silicon area used are arguably the two main critical factors that the SoC architect needs to consider when selecting the best in class data convertor for their application, once the input bandwidth requirement is met.
The choice of ADC architecture historically has tracked the end-user application. For example industrial instrumentation, sensing and audio have leveraged from the exceptionally high-precision, low speed over-sampled sigma-delta convertors. At the other end of the spectrum, where very high sampling rate and moderate to high resolutions that are typically required for data infrastructure, pipeline ADC architectures have dominated.
Figure 1. Pipeline ADC Block diagram
Arguably these infrastructure markets have been dominated by discrete data convertors, where outright speed and resolution are key requirements. These discrete convertors have certainly leveraged from the analogue benefits of the larger technology nodes, such as 0.18um. Area has historically not been a concern as the ASP’s enjoyed by these discrete convertors provided sufficient margin to accommodate the cost associated with the large die area consumed by pipeline architectures. However, more and more of these convertors are now been integrated onto deeper technology nodes. In addition due the green agenda, power, whilst historically not as important is now becoming a concern in this segment also. Hence a re-think on a more appropriate architecture is due in the data infrastructure segment.
Re-looking at the market segments once again, the highly integrated consumer segment has typically required medium speed, medium precision data convertors. However, as discussed earlier the voracious appetite for larger bandwidth at speed is pushing the requirements into the same territory as the data infrastructure segment. Additionally highly integrated consumer destined data convertors have to deal with ever shrinking CMOS geometries, from 65nm to 40nm to 28nm. Due to these geometries, mixed-signal design is moving towards big-Digital little-Analogue circuit topologies, partially out of necessity, but so too leveraging from the greater speed and integration possibilities at these deeper technology nodes. High-speed SAR ADC architecture matches this direction perfectly. It is no surprise to see the evolution, whereby high-speed SAR ADCs are replacing pipeline ADCs in this consumer segment where energy efficiency is equally important when compared to area concerns. High-speed SAR ADCs are now setting a new benchmark. It has commenced in the consumer market, with the expectation that it will move to the data infrastructure segment in time.
Figure 2. SAR ADC Block Diagram
Not alone will SAR based architecture bring more impressive power and area advantages but they will also decrease substantially the development effort by altering the design flow to become more digitally driven than analogue driven (Big-D & little-A). This removes many of the inherent difficulties of designing efficient analogue circuitry in the deep sub-micron technology nodes and therefore very substantially reduces the porting effort required to accommodate other technology nodes. This ultimately leads to a lower adoption risk, and quicker design cycle times.
To illustrate the relative performance of pipeline ADCs let’s look at the typical energy efficiency numbers and area for high-speed convertors on the market today. Energy efficiency numbers of between 300fJ and 1pJ are typical for 160MSps 12 bit pipeline architectures. Typical areas in 40nm implementations are of the order of 1mm2.
Introducing an exceptionally small, highly efficient High-Speed ADC
The S3ADS160M12BSM40LL is a 160MSp/s SAR ADC that provides class-leading energy efficiency of less than 31fJ whilst occupying less than 0.09mm2 of silicon area. Utilising a single 12-bit ADC core this convertor delivers excellent dynamic linearity performance for all cellular modems and Wifi connected devices, whilst delivering class leading power and area numbers. Currently available in 40nm processes, this single high-speed SAR ADC core consumes less than 6mW whilst utilising a mere 0.09mm2 of silicon area. Scaling this ADC down to 28nm will provide a class leading ADC core that will consume less than 3mW, whilst using less than 0.06mm2.
In summary SAR based ADC architecture is emerging as the dominant choice for the consumer SoC segment brought upon by the availablity of lower latency technology nodes and big-Digital little-Analogue mixed signal design techniques. These convertors provide vastly improved energy efficiency with exceptionally small silicon footprints. Via emerging time-interleaving techniques, SAR cores will also dominate in the communications and networking infrastructure segments.