USB 3.1 Links Pose Challenges

Tri Nguyen, Synopsys
EETimes (1/22/2015 06:00 AM EST)

The USB 3.1 spec supports data rates up to 10 Gbits/second but poses new hurdles in link-layer design for chip designers, says an expert in the IP group at Synopsys.

In 2013, USB-IF released the USB 3.1 specification, fundamentally changing physical, link and protocol players to support maximum data rates doubled to with a 10 Gbits/second. The increased clock frequency, wider data path and new 128b132b data encoding presents real challenges in implementing the link layer.

In USB 3.1, the link layer is responsible for speed negotiation, establishing the connection, ensuring the successful packet exchange, error detection and recovery, and power management. At the PIPE4 interface between the controller and PHY, the clock frequency increases from 125 MHz to 312.5 MHz for 32-bit data width to support the 10 Gbits/s rate. The frequency is even higher for 16-bit and 8-bit PHY data widths.

With a USB 3.0 link, designers could manage, especially in FPGA prototypes, to have the entire internal link data path run at 125 MHz. With additional rules and a different scrambler for 10Gbit/s speeds, designers can no longer build a link data path running at 312.5 MHz at 32-bit. The solution is to reduce the clock speed and widen the main link datapath to 64-bit or 128-bit and create a separate PHY interface unit (PIU) logic that runs at the PHY clock.

This PIU module is designed to transfer data between PHY clock and link clock. It also implements a PIPE4 protocol for all data widths (8-, 16-, and 32-bit) with a low number of combinational logic levels. While the link clock is reduced to 156.25 MHz for 64-bit, it is still higher than the 125 MHz clock for previous max 5 Gbit/s rate.

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