Ben Jordan, Altium
EETimes (1/26/2015 12:15 PM EST)
Adjusting the lengths of signal tracks so that the delays are matched and meet the DDR4 specification would be an almost impossible task without modern design tools.
The latest standard in the race for ever-denser and ever-faster dynamic RAM is DDR4, short for double data rate, fourth-generation synchronous dynamic random-access memory. DDR4 memory will operate at speeds between 1600 MHz and 3200 MHz, compared to speeds between 800 MHz and 2400 MHz for DDR3 memory. Standard memory modules will be denser, too. The DDR4 standard specifies DIMMs up 128 Gbytes, compared to a maximum of 16 Gbytes for a DDR3 DIMM.
DDR4 modules employ a hybrid topology. DDR4 designs have parallel, length-matched transmission lines for the data bus and daisy-chained, length-matched transmission lines for the clock, address, and control bus lines. The latter type of topology is sometimes called "fly-by" topology. Each signal is routed sequentially from one device to the next and is then terminated after the last device.
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