SoC testability: Designers confront speed, complexity issues
By Ron Wilson, EE Times
July 18, 2002 (11:02 a.m. EST)
For much of the lifetime of digital IC engineering, testability has been one of those issues that was somebody else's problem. But with the arrival of the SoC, it has become clear that testability rests squarely on the shoulders of the design team. If it's postponed until late in the design flow, even, the odds of problems skyrocket.
In this weeks' In Focus, several design teams describe their recent experiences with test issues. We start with a German team, from Motorola's Semiconductor Products Sector, describing the steps involved in the integration of design-for-testability (DFT) into a very fast SoC design flow for an MPEG-3 decoder chip based on a diverse collection of soft IP cores. The DFT strategy had to track changes in specification and ECOs to avoid being the critical path.
Engineers from Ethernet PHY vendor, Cicada Semiconductor (Austin, Texas), explain how a comprehensive plan for both DFT and calibration was necessary to manage the cost of a new Gigabit PHY chip. The design team offers some insights into DFT in the analog world, and the interaction between testability, calibration and full manufacturing cost.
Meanwhile, NurLogic Design's Behnam Malek-Khosravi, vice president of engineering, provides details on the test strategy for a HyperTransport PHY- a chip so fast only it could test it. And, an expert on electrostatic discharge, Brenda McCaffrey, CEO, White Mountain Labs, LLC (Phoenix, Ariz.), reviews the necessary steps that need to be addressed to insure ESD test success on a SoC. The section is capped with a strong contrary view on some of the latest fashions in SoC testability-including logic Built-in Self-Test from Tality Corp.'s chief consulting engineer, Richard Illman.