The need for more digital signal-processing power in wireless transceivers is growing. Comb filters for broadband CDMA, beam-forming algorithms for antenna optimization and multipath rejection, even bit recoding to reduce the dynamic range of OFDM signals are all demanding tasks.
Many architectures have gotten by on a single off-the-shelf programmable DSP core. But they don't make DSP cores fast enough to address today's problems, and even if they did, the power consumption would be astronomical.
So, chip architects have found themselves blending DSP cores with custom signal-processing pipelines. By assigning that CDMA comb to custom hardware, for instance, the rest of the application can be handled conventionally.
That leaves the question of what sort of hardware to use. System-on-chip designers comfortable with data path design, and wealthy enough to afford an SoC, have an obvious answer. The alternative of a custom data path gets a litt le less obvious if there is a need for multimode operation or serious doubt about the algorithms in question. But, often enough, flexibility can be built into the SoC to cover those questions.
Designers who can't justify an SoC still have the latest FPGAs and CPLDs with enormous throughput-once the algorithm is organized to take advantage of, say, 64 independent MACs in lieu of two.
Now some emerging silicon vendors are raising another alternative: reconfigurable computing. The notion is to start out with an FPGA-like device that is very easy to reprogram. Partition the application so that not all of the tasks are active at the same time. Then, at each context switch, load only the logic for those tasks that are currently active.
This is good for well-understood embedded applications. It allows you to only provide enough programmable hardware to support the largest simultaneously active set of tasks, not enough hardware to support everything at once.
There is another huge advantage to the rec onfigurable approach in one specific area: signal-strength reduction. In implementing a filter, for example, if the coefficients are fixed, you can replace a multiplier with a much smaller-and faster-chunk of combinatorial logic. You can gain much more in area and speed than you lose by using programmable logic instead of cell-based ASIC logic.
There's a catch, however. The hardware to do this kind of embedded reconfigurability has been around for several years in various forms, and almost no one has used it to do reconfigurable computing. Why? Design complexity. Thinking of the system requirements in terms of mutually exclusive tasks, developing algorithms that are optimal for implementation in programmable arrays and-perhaps most challenging-performing verification on the constantly shifting system have historically proven to be daunting problems, even in the research lab. There is little reason to believe that this architectural approach will become more tractable, let alone more popular, this time ar ound.
Ron Wilson is the Silicon Engineering Editor at EE Times. Ron can be reached at email@example.com.