By Amol Agarwal, Gaurav Goyal; Freescale Semiconductor India Pvt. Ltd.
In a current trend of SoC Design, IC’s are becoming more and more complex so the challenges of meeting all the design requirements have become increasingly difficult. Expectations from current SoC’s are low power design and reduced die size with more & more features & hence logic. Though, it is impossible to meet all of these but what designers can ensure is that try to meet all of them to the extent such that there is no loss in other specifications.
Low power consumption becomes very important in standby modes because of battery limitations. However high performance designs require faster logic gates but they are leakier and hence we either compromise on performance of SoC or low power mode targets.
There are several Power modes in any SoC:
- Normal mode: All the logic present on the SoC is working at operating frequency (high performance).
- Low frequency mode: Only a portion of SoC’s logic is working & it can be at low frequency to save power.
- Stand-by mode: Only a very limited portion of SoC’s logic is working to save power.
Dynamic power is directly proportional to frequency, and is reduced significantly in low frequency mode but leakage remains the same. The key point here is to reduce the leakage power in low frequency modes as well when high performance is not required.
Conventionally, dynamic voltage scaling is used by designers to meet above challenge. Although this solution serves the purpose to some extent but there are many overheads with these scheme
- Complex power architecture
- Timing closure challenges with multi voltage signoff
- Verification challenges.
- With low voltage supply, IR drop more stringent.
- Complex power grid constraint as grid has to design for multiple supplies.
Due to above limitations, dynamic voltage scaling is not very preferred solution to meet low power requirement. However there is one key opportunity in this problem statement which designer can exploit to meet both high performance and low power requirements
Any logic which is supposed to run in low frequency mode is also made to run in normal mode at a high frequency and hence the same logic has been signed-off pessimistically to operate on high frequency. So, same logic when operates at low freq. provides huge timing slack which can be utilized & proposed circuit is using that opportunity with substantial power savings.
Current high performance design looks like as below (Fig. 1):
As the number of fingers in any cell increases then delay decreases with increase in power. Since, the same cell is required for high-performance as well as for low-performance but would have same leakage power.
Fig. 1 Conventional cell design
Idea is to design a Dynamically controlled logic gate which can be dynamically adjusted to provide High speed with more power OR low leakage with more delay SoC requirements so that high performance and low power designs go hand in hand. Below is the proposed circuit (Fig. 2)
Fig. 2 Proposed cell design
This is applicable to any combinational logic gate with more than ‘1’ fingers i.e. n >= 1 where ‘n’ is the no. of fingers (finger is the maximum size of the transistor which can be made within the fixed height of the layout).
‘1’ to ‘n-1’ fingers can be programmed as per the proposed circuit to achieve the desired gain.
Working of the proposed circuit:
When EN = 0, it works similar to the conventional cell & is also similar with respect to the delays & power. When EN = 1, it works only through transistors M1 & M2 (as in Fig. 2) & hence more delay is achieved with less leakage & there is no need of high-speed in low frequency operation.
Table1. Spice results between conventional & proposed circuit (when “n – 1” fingers have been controlled with EN signal)
Table2. Spice results between conventional & proposed circuit (when only “1” finger has been controlled with EN signal)
It is clear from the above analysis, that there is a considerable savings (~3.5 %) in the leakage power dissipation for the proposed circuit when EN = 1 i.e. in Low power mode for only ‘1’ finger programmed (as per Table 2) & (~65 %) in the leakage power dissipation for the proposed circuit when EN = 1 i.e. in Low power mode for “n – 1” fingers programmed (as per Table 1). All designs can use the proposed design architecture. The proposed idea is very flexible and provides designer multiple flavors (fingers controlled with ‘EN’) of dynamically controlled logic gates for a given logic gate as per the need.