By Srinivasan Nachiappan (Mindtree)
This paper describes a CSoC platform and configurable digital subsystem IP which can be deployed for development of IOT edge devices. The paper encompasses the different attributes of IOT edge device that can cater multiple industry segments, key features and benefits of CSoC platform, components of the digital subsystem IP that enables rapid prototyping of SoCs for IOT applications.
ERA of IOT
IOT simplified is a global application where devices can connect to the host of other devices and exchange valuable data for efficient decision making. Data consolidation and analytics typically happening on a cloud environment paves way for creative & value added services / improving efficiency and optimizing cost. This overall improvises standards of business execution and adds economic value at all levels. This emerging market impacts semiconductor devices, system OEMs, cloud service providers, and internet infrastructure companies. Industry predictions are around 50B devices getting connected by 2020. Reports by Yole Development pegs the market size in the $70 billion range by 2018, with the next five years presenting a golden opportunity for device makers as the IoT enters the growth stage. By 2024, the report predicts that overall market value for components will exceed of $400 billion, of which more than 10% will come from hardware alone.
Expected Growth in Units / Semicon Business driven by IOT (Web-Search)
Hypothetically IOT applications are very diverse with multiple opportunities with innovative products but when confined under a realizable and marketable model, they can be broadly classified under the following industry segments.
- Consumer (Wearable)
- Health Care
- Home & Business Automation
- Smart Cities
A typical IOT eco-system can be envisioned as conglomeration of three entities - Devices / Gateways / Network & Cloud. While the Device and gateways uses any of available standard wireless or wired technologies for data communication, the gateways and Network & Cloud uses the existing internet infrastructure.
Attributes of IOT Edge Device
A typical IOT edge device can be considered as integrated sensor and actuator hub, backed by an embedded processing unit with connectivity solution for data transfers with the gateway / internet. The device hosts a processor core with optimal compute power to perform the required embedded processing. The device also integrates necessary digital peripherals (IPs) including connectivity IPs and analog sensors (IPs) to meet the product requirements. As security is paramount the device comprehends multiple levels of HW & SW level security features to avoid breach of the device while providing an efficient user interface for a rich user experience.
Attributes of an IOT Edge Device (Web-Search)
The end application and deployment of the device plays a vital role in driving the requirement specification of the SoCs / System-In-Packages in terms of architecture, methodologies all the way till packaging. It can range from making a simple analog sensor hub smart to high end device performing intense computation and running multiple applications in parallel. Few of the key parameters / knobs are as listed below.
- Processor Core
- Single / Multi - Core
- MIPS Rating / Maximum Operating Frequency
- Closely Coupled Memories (TCMs / CCMs)
- HW Accelerators
- Memory Sub-System (Internal & External)
- NVM / ROMs / SRAM / DRAM / FLASH
- Patch System
- Bus Fabric
- High Performance Bus Controllers (Multi Master - Multi Slave)
- HPB 2 LPB Bridges
- Digital IPs
- System / General Purpose Peripherals
- Connectivity / DFx
- Analog IPs
- System / Peripheral Operating Frequencies
- Technology Node / Optimized Libraries
- Ultra Low Power
- Multiple Power States / Voltage Domains
- Cohesive HW - SW Development
Mindtree’s CSoC platform paves the way for rapid development of SoC’s targeting IOT applications. It is processor core and bus fabric agnostic and enables rapid development of SoCs using any processor core, bus fabric, multiple memory sub-system configurations, multiple peripheral IP’s with various configurations. The core of the CSoC platform is a Digital Subsystem IP which comprehends most of the general purpose IPs required for SoC development targeting IOT edge devices. The general purpose IP’s are highly configurable and PPA (power / performance and area) optimized for an optimal SoC solution. The platform provides a robust co-verification platform to verify the IPs and the SoC easily. It also provides a framework for performing the FPGA and ASIC-FE flow flush to ensure the implementation flows are smooth. The eco-system also provides a prototyping platform to validate the SoC that eases the process of compiler integration, developing device drivers, diagnostics, BSPs and application enabling a cohesive HW - SW development. It also provides a utility frame work for easy 3rd party IP (DIP / VIP) integration in to the platform. The complete development is automated through utilities for SoC integration, Co-Verification environment generation, FPGA & ASIC-FE flow flush and developing diagnostics for validation. In summary the CSoC platform proves to be an ideal framework for rapid development and prototyping of SoCs for IOT.
Configurable SoC Platform Development Suite
The key differentiators and uniqueness of the CSoC platform which sets it apart from other similar solutions in the industry are its
- Support for ANY Processor Core
- Support for ANY Bus Fabric (with protocol specific bus wrappers)
- Technology Node Independence
- Comprehensive & PPA Optimized Design IP (corresponding VCs) Portfolio
- Easy 3rd Party DIP (HIP / SIP) / VIP Integration
- Test Re-Use Methodology
- C & SV based Co-Verification Environment
- Seamless Migration from FPGA Prototyping to Silicon Bring Up
- Cohesive HW - SW Development
- Implementation Flow Flush
- Automation Utilities
Architecture - Digital Subsystem IP
A typical SoC consists of an Analog Core, Digital Core and Test Infrastructure. The analog core contains all the analog blocks required for the SoC that controls the power, frequency, data conversions required in the chip. The analog core consists of FUBs like POR, PLLs, ADC, DAC, battery detector & charger, voltage regulators, and oscillators etc. The digital Core in SoC consists of processor subsystem and digital subsystem IP making it truly modular to cater any processor core for the SoC. The Digital Subsystem IP consists of HPB controllers, LPB bridges, peripherals IPs (both masters and slaves), memory subsystem – RAMs and ROM etc. The various test infrastructures including JTAG, tap controllers, MBIST controllers, custom BIST and boundary scan are also comprehended as part of digital subsystem IP. The Design IP portfolio encompasses all general purpose IPs with adequate configurable options with different bus wrapper (to make them bus fabric agnostic), different frequency relationship, IP specific configurations. Such a generic Digital Core can be envisioned as depicted in the diagram below.
Digital Core / Digital Subsystem IP
Platform provides a comprehensive DIP portfolio mix of them would constitute the Digital Subsystem IP targeted for a particular IOT edge device. The various DIPs provided by the platform are briefly discussed below.
On-Chip Memory Controller
The on chip memory controller IP provides the ROM/RAM interface for the on-chip memories. It supports 8 / 16 or 32 bit width accesses and zero wait states for memory accesses.
The patch system IP complements memory subsystem by providing a method to de-risk the code (ROM) freeze and supports up to 16 patches in the SoC. The patch configuration space can be populated during boot up using an external EEPROM device or a FLASH ensuring a work-around infrastructure.
The system controller IP provides the reset control and clock management framework for the SoC. It employs dynamic clock gating, clock switching, frequency scaling and oscillator control features which the software can exercise to achieve optimal power consumption.
The interrupt controller IP controls the interrupts and its scheme in the SoC. Up to 32 interrupts can be configured with individual programmable input / output interrupt mode / logic levels. It also provides the flexibility to be configured for normal / fast mode or individual interrupt mode based on the processor core.
Power Management Controller
Low power requirements are a defacto standard for IOT edge devices, and the generic programmable power management controller provides the necessary hooks required to realize and exercise various power optimization knobs embedded, exercise various power modes, power switch controls and handle custom sequencing required between different power states of the device.
The DMA Controller is used for data transfers between peripheral devices to internal (or CCMs / TCMS / external) memory without processors intervention. This relives the processor to perform intense algorithmic & processing within the core in parallel. This in turn helps is maximum utilization of the BW on-chip and on-core when the device is active.
Timer / Watch Dog Timer
The timer/watch dog timer IP provides the base timers used by the software and watch dog functionality. The IP can be configured for timer/ watch dog timer functionality, reset/interrupt generation and one-shot/cyclic mode of operation.
Real time clock is another defacto feature most of the IOT edge devices. This IP is a typical Always-ON IP that is designed to consume the least power with features of day-light savings / zones etc as embedded in most IOT edge devices.
The GPIO IP provides the MMI (man machine interface) for the system and can be configured up to 24 ports. The IP provides flexible pin multiplexing options for various special functions which results in optimal number of I/Os for the SoC. It provides configurable options for I/O logic level, long & short press, pull up & pull down controls and de-bouncing circuitry.
The UART IP provides the connectivity to various sensors in IOT edge device. The IP provides programmable baud rate generation up to 1Mbps, independent TX / RX buffers with programmable threshold settings, configurable flow control and interrupt modes.
The serial peripheral interface IP is used to interface with external SPI EEPROM which may encapsulate the IOT application related parameters, code etc. It can also contain the patch code which can be copied to the on-chip RAM and executed. The IP can be configured for 3 / 4 wire interface, different address / data widths / formats and interrupt modes.
The I2C IP is used to interface with external I2C EEPROM which may encapsulate the IOT application related parameters, code etc. It can also contain the patch code which can be copied to the on-chip RAM and executed. The IP can be configured for master / slave mode and different interrupt modes.
Pulse width modulator, used to generate variable pulse width for audio / motor control applications. In case of audio applications they drive external speaker stage through the processed I2S audio data and in motor control applications it controls the external motor relays.
I2S is used for especially used for IOT SoCs with audio application. The I2S IP takes serial data input from audio codec and buffers the data for the embedded audio processing to be performed by the processor core. It supports a range of configurable features including different data rates and data widths.
Connectivity and especially wireless is a key attribute of IOT edge device. Though there are many low power technologies like ZigBee, LoWPAN, NFC and Bluetooth that one can rely on, low energy Bluetooth is the most prevalent protocol deployed across multiple products which form the HUB or the gateway for IOT devices (smart phone, tablets etc). BlueLite is Mindtree’s single mode Bluetooth® Smart (v4.1 and v4.0) which constitutes the Baseband Controller and Digital PHY.
Mindtree’s EtherMind is software IP for both Bluetooth Smart and Bluetooth Smart Ready, which consists of stack, profiles and application frameworks for Bluetooth versions 4.1, 4.0 and 2.1+EDR.
*For more information on Mindtree’s Bluetooth IPs visit http://www.mindtree.com/services/engineering-rd
CSoC eco-system provides a comprehensive C and System Verilog based co-verification environment for verification of integrated DIPs and the SoC. The C based test cases are developed using actual drivers of the DIPs. The platform supports integration of any 3rd party HDL or HVL based VIP models. The platform also supports IP band width analysers, bus utilization which supports software profiling and performance estimation. The coverification environment supports easy compiler integration for various processor cores, effective test bench communication and control via a proprietary VPI (Verification Platform Interface). The essential components of verification are Processor Compiler Engine, Processor Compiler Interface, Test Bench Peripherals, VPI Engine, System Memories, External Peripherals and Models.
CSoC Verification Environment
CSoC framework adopts an innovative TRM for effective test case development and re-use. The C test cases are developed over the actual drivers which can be used for the peripheral validation and product development. The seamless usage of drivers makes ensures flawless and rapid development of product software. The test cases developed using TRM deploys VPI for verification in the co-verification environment, UART interface for IP validation. Upon validation of the IP’s using the same drivers used in the verification, the device drivers supports in rapid low level firmware development for the product.
Test Re-Use Methodology (TRM)
Validation Platform (in works)
CSoC eco-system also provides a validation platform for IP / SoC validation. The validation platform supports in prototyping the SoC (digital subsystem) and software development. The platform is designed to suite prototyping to any FPGA vendor and device family. The platform also provides support for integrating application specific hardware through daughter (extension) cards. It also supports Analog components equivalent to Analog macros in the final SoC, which provides an ideal prototyping of the final SoC. The platform can also be used as an ASIC validation platform by replacing FPGA daughter card by the ASIC’s equivalent providing a seamless migration of the evaluation from FPGA prototyping to ASIC realization. The validation platform also supports a standard micro-controller which enables to use the platform for any general purpose development or as an external host. The platform also provides hooks for battery mode operation and power measurement enabling power estimation of the solution.
CSoC Validation Platform
Cohesive HW - SW Development
Developing SoCs / solutions and products for IOT requires a cohesive HW - SW development with various system considerations both at hardware and software layers to meet the requirements specification of the end product. Typical system considerations at hardware layers include gate count of IPs & SoC, accelerators, low power features & states, memory requirements, frequency scaling, voltage domains, DFx area overhead, overall die area, package and PCB form factors etc. Typical considerations at software layers include code size (boot / service routines / device drivers / middle ware / applications / OS), memory requirements, interrupt response latency, code optimization for area / power and exploiting low power features of the SoC. CSoC platform and methodologies paves way for a cohesive HW - SW development ensuring exploitation of various features in hardware and software in parallel for an optimal IOT solution.
CSoC Platform / Digital Subsystem IP in IOT System Development
Flow Flush - ASIC / FPGA
The CSoC eco-system provides the framework for performing ASIC / FPGA flow flush at IP / subsystem (or SoC) level to ensure smoother prototyping of the SoC on FPGA platform and ASIC migration. All DIPs are flow flushed for both ASIC (synthesis / DFx realization / MMMC implementation & timing closure / PV & RV) at a chosen node / FPGA (synthesis / implementation) development cycles to ensure silicon readiness. The seamless migration between FPGA prototyping and ASIC silicon evaluation using same validation platform significantly reduces EVM costs and time to market.
The platform provides ample automation utilities for automating SoC integration, verification environment creation & integration at IP / SoC levels, ASIC / FPGA flow flush template generations for various phases to ease SoC designers. The automation helps in significant reduction of engineering effort, faster development and easing hand-offs between various streams providing foolproof methodology for SoC realization.
For rapid and successful product development of IOT edge devices IDMs / OEMs can start with digital sub-system IP customization & enhancements, 3rd party IP integration (digital / analog) to realize the SoC. The drivers and relevant SW stacks can be developed / integrated with processor specific IDE environment that can be easily coupled with CSoC framework. The SoC can be further FPGA prototyped / emulated at application levels before ASIC realization takes-off and the CSoC platform is highly conducive for such a collaborative effort.
The key for successful SoC development for IOT edge devices is choosing a cohesive HW - SW development platform with appropriate tool kits / flexible and scalable features for integration and prototyping. In that context CSoC platform and the digital sub-system IP provides maximum flexibility for the system architects to provide low cost solutions for IOT edge device applications. The solution significantly reduces engineering effort and enables faster development and prototyping of IOT SoCs that enable customers to make & take their compelling products to the market. The approach also reduces derivative engineering effort incurred during development of derivatives for diverse IOT applications.
My sincere thanks to Mindtree’s VLSI Sub-Service Line / CoE team and management for their long term conviction on this platform’s vision, strategy, methodology and its benefits. Appreciate the efforts and tenacity of the execution team members in development of the platform and realizing a PoC.
About the Author
Srinivasan Nachiappan, Technical Director - VLSI - Mindtree Ltd holds bachelor’s degree in ECE (Electronics and Communication Engineering) from Madurai Kamaraj University and masters in Micro-Electronics from BITS - Pilani, India. He has 15+ Yrs of VLSI experience in handling and executing various streams in ASIC / FPGA designs. His core competency and interests are in IP / SoC development and sub-chip / full chip executions.
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