Ken Brock, Synopsys
EDN (April 13, 2015)
In September 2014, TSMC released its third major 28 nanometer (nm) process into volume production—28HPC. Millions of production wafers have come out of TSMC’s first two 28-nm processes (the poly SiON 28LP and high-K Metal Gate 28HP/28HPL/28HPM). With 28HPC, TSMC has optimized the process for mobile and consumer devices’ need for balance between performance and cost. Using a combination of this process technology and high-quality standard cell logic libraries designed specifically for this process, designers can achieve their performance, power and area goals while mitigating schedule risk.
This article describes five areas where designers can take advantage of this new process with the latest logic library technology to optimize the performance, power and area of their system on chips (SoCs). First, designers can improve SoC performance by using the global slow and fast (SSG, FFG) signoff corners enabled by TSMC’s tighter process controls with 28HPC. The improved performance enables the use of lower drive (smaller) logic cells to close critical timing paths. Second, the 28HPC process reduces area, and therefore cost, as relaxed process rules enable library providers to deliver shorter cells with improved routability. Third, these same relaxed rules enable longer channel lengths to be drawn than could be drawn with the 28HPM process to reduce leakage power by up to 50% without use of expensive lithography-based gate biasing. Fourth, TSMC’s tighter process controls for the 28HPC process cut power consumption by reducing leakage by 20% in its corner models. Fifth, new logic library features introduced for the 28HPC process, such as multi-delay, multi-setup and multi-bit flip-flops (MBFF), help designers optimize their processor cores for performance and power. The combination of innovative process technology and library design capabilities along with the latest EDA tool innovations and flows enable SoC designers to use their design skills to produce the highest performance, lowest cost designs consuming the lowest power.
Click here to read more ...