Ron Wilson, Altera
May 18, 2015
The appearance of subsystem-scale intellectual property (subsystem IP) cores a few years ago triggered a glacial shift in system-on-a-chip (SoC) design: slow, inexorable, but shoving before it a mound of unintended consequences. As cell-based SoCs and even FPGAs incorporating subsystem IP appear in real systems, we are seeing that those consequences extend even beyond the boundaries of the chip.
The concept of subsystem IP is unassailably appealing—it is simply an extension of design reuse further up the hierarchy. If reusing an interface block is good, why not reuse an entire audio subsystem, or machine vision subsystem, or whatever? In effect, we are picking up an entire modest-sized SoC, including its CPUs, accelerators, memory hierarchy, I/O controllers, and external interfaces, and instantiating it inside a larger chip.
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