Parasitic Extraction of FinFET-based Memory Cells

Karen Chow, Mentor Graphics Corp.
5/25/2015 10:20 AM EDT

Memory chips must meet strict specifications for fast data transfer, reliability, and power consumption, so accurate characterization is required at every stage of design.

The introduction of FinFETs at 16 and 14 nm nodes enables higher density and performance, and reduced power usage, but it also increases challenges in design and validation. Memory designers need a tool that can help them analyze parasitics quickly and accurately throughout the design cycle.

Introduction to FinFETs

FinFETs are three dimensional structures that rise above the substrate and look like a fin, hence the name. Theses fins form the source and the drain, and the gate wraps around the source and drain, providing better control of the channel.

When the device is in the off state, there is very little leakage current. With FinFET designs, there is low threshold voltage, and a lower supply voltage can be used. This drop in supply voltage results in reduced power usage while maintaining performance.

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