Naveen Srivastava , Rohit Ranjan & Amit Bathla (Freescale)
EDN (June 04, 2015)
One of the major issues faced in the verification of analog or AMS IP in the SOC environment is the behavioral model’s limitations. Since behavioral models are not perfectly able to replicate analog behavior in a verification environment, many critical bugs are left uncovered.
We will be focusing on this problem, and will discuss how to achieve more accurate analog behavior by using a structural netlist instead of a behavioral model to reduce the number of silicon defects and the verification cycle time.
SPICE model netlist conversion to structural netlist
This approach talks about using methodologies which directly convert transistor level SPICE model into Structural netlist. The principle of these methodologies is to work by isolating Analog circuits from logic and automatically recognizing the latch and flip-flop structures. The design is partitioned into cells, and an automatic algorithm on pattern based function extraction is run. The output is a structural netlist which is used in place of behavioral model for verification purpose. The structural netlist so obtained is pretty much close to actual analog SPICE model.
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