A silicon virtual prototype is key in achieving design closure

The RTL SVP is a physical model of a chip based on pre-characterized RTL structural elements. It gives RTL designers the earliest possible visibility into whether their chip will meet area, timing, and power targets for a specific DSM process technology. By integrating the RTL SVP into an interactive analysis environment, designers can pinpoint RTL and constraints that cause downstream timing or layout problems. Since RTL quality impacts a chip's final implementation quality, early detection of RTL code that causes downstream gate-level problems is a high-return activity.

The gate-level SVP provides a finer-grained, more accurate physical model of the chip as compared to the RTL SVP, but at a cost: turnaround times are significantly longer and designers need to have significant layout expertise. Starting from a gate netlist, the gate-level SVP lets designers layout clock-tree and power-bus top ologies as well as produce gate-level placements and other implementation details needed to get layout-accurate timing and area information. Coupled tightly with a gate-level physical synthesis tool, the gate-level SVP provides the floor plan and parasitic information needed to accelerate gate-level design closure with placed gates.

So which one of these SVPs is the "real" SVP? The greatest value comes from leveraging all three in an integrated flow. Because the ESL SVP has no physical data, ESL tools must generate RTL to enable an RTL-SVP-based analysis. Using the RTL SVP to identify micro-architecture inefficiencies, RTL designers can anticipate and avoid downstream gate-level timing and layout problems without getting tied up in the intricacies of a gate-level floor planner. The hierarchy partitions, timing budgets, and floor plan constraints from the RTL SVP are then fed forward as initial conditions to the gate-level SVP. This improved starting point for gate-level implementation eliminates unn ecessary, costly iterations. Should the gate-level SVP indicate that design objectives cannot be met, regardless of the physical floor plan, the gate-level SVP feeds back its physical placement information to the RTL SVP for further RTL analysis. This automated top-down bottom-up flow is actually a methodology that has been followed successfully for years, albeit manually, by designers of high-performance chips.

Experience by our customers has shown that employing RTL SVPs is a breakthrough because of its higher-level design abstraction. It yields increased design capacity, turnaround time, and a simpler analysis environment compared to the gate-level SVP. Waiting until a design is elaborated to the gate level before detecting RTL inefficiencies or improper constraints requires significantly more effort because of the increased design and analysis complexity. When design closure is obtained with the RTL SVP, handoff to gate-level implementation can be done with greater confidence. This is just one r eason why Gary Smith of Gartner/Dataquest has stated, "the silicon virtual prototype is the key that unlocks the future of design, and the world of EDA will never be the same."