Design closure becomes elusive for the SoC generation

The question has no definitive answer — designers and b usiness planners try to establish a method and a set of specifications that can somehow contain the problem within probabilistic limits. The stark fact of the SoC generation is that no one will ever really know with absolute certainty that a given circuit really will perform exactly the functions for which it was designed.

The difficulty of the problem has forced design teams to think ahead, working design verification and test elements into a project right from the start. Rather than going straight for the optimal performance and die size, there is a growing recognition that getting it right the first time may have more impact on product success. Appearing side by side with smart ideas for optimizing power, performance and silicon real estate, strategies for achieving closure on the critical aspects of a circuit have become a new measure of excellence and design expertise.

In this week's Silicon Engineering series, engineers from Verplex Systems and CCube Microsystems discuss a method for achieving functional closure on large RTL designs. Their strategy uses a method called property checking that can be built into a design from the start. A design property is a logical proposition about correct behavior that can be automatically extracted at the design verification stage to speed the verification cycle while amplifying confidence in the correctness of the result. Circuit designers can use the method to head off many verification problems by working with properties early in the design cycle.

Aiding this approach is a set of standard assertions being hammered out by a standards organization, the Open Verification Library (OVL) initiative, that reduce design properties to a standard set. This system is ideal for insuring that circuit blocks designed by different teams can be guaranteed to work properly together, since the critical interface components can be checked with standard assertions and automatically extracted properties.

In an exclusive online contribution, Richard Go rdon, executive vice president and a cofounder of Tera Systems, Inc. (Campbell, Calif.) presents his rationale for using a technique called silicon virtual prototyping to ensure that designs are on track. The new approach, which is becoming quite popular in the EDA industry, uses a set of predefined elements to characterize a design. For example, at the register transfer level (RTL) a design would be encoded in predefined and fully characterized RTL elements, allowing a design team to test their efforts against a realistic scenario of RTL closure early in the design cycle. Virtual prototypes also exist for the system-level view of a design and at the lower gate-level view. Gordon concludes that the RTL level is critical for achieving overall design closure.

And, in another exclusive online contribution, a group of engineers at STMicroelectronics, Inc. Central R&D Center in San Diego, California describe their bid to build a microprocessor core that can be guaranteed to run as fast as a standalo ne chip. They chose an industry standby - the original Inmos Transputer architecture - as a takeoff point for soft-portable CPU that can be dropped into embedded SoC designs. Called the iCore, the resulting design reworked many of the standard features of the Transputer, which is close to a RISC design, in order to get easily synthesizable design that could be verified with standard tools typically used in ASIC design flows.

The design challenge was to demonstrate the feasibility of achieving full custom performance using standard ASIC design flows. The design had to be fully portable as a soft-core across existing and future technologies.