Shahab Akhtar & Piyush Mishra (Freescale)
EDN (June 17, 2015)
SOC design comes with its own set of complications and challenges. One of the biggest challenges that arise is inherent limitation of particular technology node. As technologies are scaling down, it is becoming more difficult to design the power grid for power hungry SoC with limited power source & inherent limitation of particular technology node. In deep sub-micron technology designs, IR drop can often significantly impact the functionality. In this paper, a new methodology is introduced which results in a very robust power grid structure. Along with the robust design techniques, this methodology results in better silicon results.
Basics of power grid structure & limitations
Power delivery network (PDN) is the heart of any SoC which supplies power to the entire design. Power grid design of system on chip (SoC) is very important element to build efficient PDN. Power grid should be created such that the worst voltage drop must be meeting across the SoC.
Metals used in the power grid mostly depend on the power requirement of the design & also it depends on metal options used in the technology node. More metal option cost more but it will create more robust design than less metal option design. Metal usage (width, spacing, and metal stack) in the power grid is defined by the power requirement. If we have more power requirement, then in this case we must use metal of more width for the grid. Metal width should be chosen such that no routing track is wasted. Sometimes DRC rules also play a role in deciding the power grid metal width.
Let’s have a look on the DRC spacing sample, table 1. DRC spacing rule depends on the metal width & also on the parallel run length of the metal. Below spacing table shows that how spacing varies. If we take M4 power stripe width of w2 um, then in this case spacing from the next M4 signal route of width w1 um (minimum metal width of M4) must be of “s3”. M4 width “w2” is chosen to take-care the wide metal rule so that we don’t waste the nearby routing track. We are assuming routing grid is of “x” for a particular technology node which may vary from technology to technology. Inherent limitation of technology node forces to leave a gap of 0.01 in both side of M4 power stripe to meet DRC rule. It’s called “technology gap”. In this way 0.02 um (0.01+0.01) of useful metal resources has been wasted on every M4 stripe of power grid in existing approach. For bigger die size, this technology gap makes significant impact on the grid utilization & it leads to sub-optimal use of power grid. This technology gap may vary as per power grid metal width selection.
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