Introduced decades ago, Ethernet technology has become truly ubiquitous, entrenching itself into every facet of our everyday lives including our homes, cars, and factories. The technology benefits from reliability and robustness built over this period of decades, and a very vibrant and active set of IEEE 802.3 working groups who are continuously optimizing and tailoring it for emerging applications. The Ethernet Physical Layer has been and will always be the corner stone of system design, being the point of communication among different chips and/or boards within and across different systems.
In accordance with Moore’s Law, semiconductor devices are typically introduced in successive generations which integrate more features and have lower power. This trend has driven the advancements we see all around us today. However, despite a relentless industry trend towards miniaturization and integration, the Physical Layer of the Ethernet protocol has survived on system boards as a discrete component, supplied by one of only a handful of vendors, selling relatively antiquated and power-hungry discrete solutions.
In this paper, we will look at the economics of integrating the Ethernet Physical Layer, and what options exist for product managers and engineers seeking to shrink their power and area footprints, while achieving cost reduction
Moore’s and More
Moore's Law has helped to build the expectation of consumers that future electronic devices will be increasingly smaller, have more features, and greater battery life than previous generations. Furthermore the more interactive experience of today's average users implies that even more highly integrated components within a device are active simultaneously – as new features or connections are added, new semiconductor content is being required. Another important aspect which is now imperative with mobile devices is that the total weight and / or “slimness” of the product must be within certain levels in order to maximize its appeal to customers. To help meet these expectations' a substantial level of system integration is being required at all levels. Typically as features have matured, they have become integrated into SoC through the use of 3rd party IP. The IP model allows SoC designers to focus on their own capabilities, and leverage the interface-design talents, and scale, of outside companies. However, the Ethernet PHY, one of the most mature computer interconnection technologies available, has until recently resisted this integration trend. Why is this?
First of all, third-party IP, which is often a key driver of integration, has been relatively scarce. This is because the traditional IP vendors often have a core competence in EDA and digital design, and a poor match for providing complex Ethernet PHY’s as IP. Compounding things for the traditional players, SoC vendors require varied process alternatives, driven by cost and performance requirements of their core businesses, with schedules typically 6 months or less. The mainstream IP vendors are unable to keep up to these technical and schedule requirements. From an IP perspective, what was needed was an IP specialist, who could address the complex requirements.
Alternatively, SoC designers could have tried building their own teams to develop the IP in-house. However, this would require considerable expertise and foresight, and likely locking the SoC vendor into a specific process for a long time. Developing a technologically advanced design like a Gigabit Ethernet PHY from scratch is such a big effort, that in a mature and consolidated market that most customers previously had to accept undesirable off-chip implementations rather than highly integrated solutions. This has caused companies suffer increased costs, larger boards and wasted power.
OmniPhy – “Ethernet as IP”
Several years ago, OmniPhy, a specialty IP company with emphasis on advanced mixed-signal design and digital signal processing in physical layer connectivity, invested heavily in helping customers tackle this problem. In 2012, the team developed the first EEE compliant 28nm Ethernet PHY on the market and made it available for general industry use. Since then, the concept has spread like wildfire, and the company has successfully put 10/100 into volume production across several process technologies, making the technology available on modern process nodes. SoC vendors can now choose from a variety of process technologies, knowing that their IP is reliable and silicon proven. The Ethernet-as-IP model enabled by OmniPhy changes the game for billions of devices and enables a new paradigm in system integration.
Helping You Lower Costs and Improve Margins
Integrating the function drives significant bill of materials savings, board and material assembly savings, and allows for smaller form factors.
The following table illustrates how much revenue is being lost for a discrete IC:
Cost Per Chip (USD)
Discrete IC and it’s BOM (volume)
Incremental Assembly Cost
Table 1: The high costs of discrete Ethernet PHY
From the table we can see that for a modest run of 25M chips, $11.5M (USD) is lost. Of course, the SoC die area must accommodate the feature, and the cost of IP, however since OmniPhy leverages the cost across dozens of customers, economy of scale is achieved. Design managers are often surprised at how small the area is because these designs are optimized on advanced process geometries.
In the final analysis, the decision to integrate the Ethernet PHY is analogous to the FPGA vs SoC trade-off: for low volume and prototyping applications, buying discrete IC’s will make sense. However, in even modest volume production, the integrated approach is the winner hands down, driving millions of dollars in savings for suppliers and end customers alike.
Design complexity and IP availability limited the integration of the Ethernet PHY layer for several years, driving higher costs across the industry. However it is now possible to harness the power of the IP model and integrate silicon proven IP directly onto the SoC, achieving higher total gross profit compared to a discrete PHY IC option. Higher system integration by bringing on-chip the physical layer was once an excluded route for many SoC vendors, but today the OmniPhy expertise is at your disposal to help you achieve this challenging goal.