Ron Wilson, Altera
The arrival of FinFETs, starting in the 20 nm CMOS logic process node, has been justly credited with saving Moore’s Law. Just as our ability to continue scaling planar MOSFETs began to come apart, the FinFET’s vastly superior channel control came to the rescue, taming leakage currents and opening the way to continued voltage scaling. The timely intervention allowed Vivek Singh, keynoting at the Design Automation Conference this month, to claim that through the 14 nm node Intel has maintained a steady improvement in transistor speed-power curves.
With leakage under control of a gate that drapes over the fin-shaped transistor body on three sides—hence Intel’s preferred term, Tri-Gate—device designers are free to continue reducing operating voltage and critical dimensions. This liberation has continued through 14 nm, and promises to persevere through 10 nm and beyond, albeit supported by increasingly radical device engineering and by new materials. At the recent TSMC Technology Symposium, for example, TSMC vice president of R/D YJ Mii said that beyond 10 nm, his organization is looking still at FinFETs and their near relatives, gate-all-around FETs, but perhaps with fins of germanium or indium gallium arsenide.
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