Building world-class Network-on-Chip interconnect IP and configuration tools is difficult, time consuming and capital intensive
Charlie Janac, President and CEO of Arteris
There was a time when developing the on-chip interconnect was much simpler. Today, however, building world class interconnect IP has become complicated, lengthy, capital intensive and resource intensive. The question is, can design teams build an interconnect fabric internally that not only meets the requirements of the most advanced System-on-Chip designs, but is also fully verified every time? Or is it more practical and expedient to acquire interconnect IP from a third-party and configure it to the unique needs of the SoC? All of the hard facts about interconnect development should be considered before answering these questions.
In the past, centralized crossbar and bus interconnects could be built by 5- to 15-person engineering teams with budgets of around $4-7 million per year. But then the world became more complex. With the arrival of 40nm processes, SoC semiconductors grew in size and complexity. Mobility, digital TV and solid state storage SoCs now contain over 100 IPs at the top level of hierarchy. In addition, they have multi-core CPU subsystems, multiple power and clock domains, special purpose accelerators, and heterogeneous transaction protocols from different IP suppliers.
Figure 1. Hundreds of IP and dozens of heterogeneous transaction protocols are linked together in SoCs by the network-on-chip interconnect.
And the challenges only get more profound. With newer IoT edge client designs, the chips are not complex in terms of die size but are very complex in terms of power management. Obtaining multiple weeks or months of battery life through power scavenging techniques requires advanced interconnect IP technology to finely control IP block and clock tree power usage. And as process nodes shrink to 10nm and below, soft errors due to everyday cosmic radiation may force the use of parity bit and resilience techniques in mainstream SoC designs to maintain data integrity, similar to how ECC, parity and unit duplication are used for today in mission critical automotive and industrial SoCs to guarantee functional safety.
Any team designing SoCs in 28nm and below needs to be aware of some critical aspects interconnect IP when they are planning their next project. Doing so will enable an appropriate allocation of resources and ensure the project achieves successful tapeout.
The interconnect is much more than just wires!
Any state-of-the-art interconnect will deliver the following requirements:
Performance, power and area efficiency.Silicon is never free in volume semiconductor markets where competition is fierce. The typical interconnect IP is roughly 8-12% of SoC area so minimizing wires and gates has a significant impact on SoC die size and therefore cost. The larger the SoC, the larger the impact. Idle power, clocks on but no data traffic, has a major impact on battery life. Excessive interconnect IP power consumption limits battery life. Excessive latency leads to poor marketing benchmark results. No one wants to put an uncompetitive interconnect in their SoC these days. It is a matter of competitive advantage.
Figure 2: Power vs. Performance across interconnect configurations
Broad range of interconnect IP design tools improves SoC design productivity. These tools must help design team members in many phases, from architectural exploration/simulation to RTL generation to verification, physical awareness, silicon debug and bring up. The more configurable the IP, the more important the tooling. This requires strong software and EDA-type development capability. Interconnect IP hardware also has a major impact on productivity because it connects to the rest of the IPs in the SoC while implementing SoC services such as Quality of Service, Power Management and Hardware Security. Getting SoCs to market due to lengthy interconnect IP design iterations can cause a company to lose design wins and market share.
Comprehensive verification capability: This should cover unit verification, module verification, SoC level verification, tool verification, IP design flow verification, IP and EDA partner interoperability testing, customer SoC design-in and end customer system deployment. Quality problems at any level will impact productivity, schedules and end-product quality. See Seven Levels of Verification EDN May 2015. The reality is it takes a long time to verify a home-grown, custom interconnect, and impacts entire product lines when the need to verify interconnects for derivative chips is accounted for.
Customer project validation requires not only a flexible architecture, but also global support, professional documentation, the ability to deliver rapid enhancements and bug fixes, and an architectural design review prior to tapeout. Customer support requires not only developers but also professional application engineers with SoC design backgrounds to help users.
Investment: Meeting these requirements requires money, people and experience
Creating a new interconnect is an inherently risky, long-term investment. All of this is costly. An internal team building a Network-on-Chip interconnect for use in multiple SoC designs will need 25 to 50 engineers plus a team of application engineers to support internal users. With fully-loaded engineering cost, a company is looking at a $7-to-15 million annual investment, which can add up to $42 million to $60 million for the minimum six-year development and maturation cycle. It is rumored that one SoC maker has an internal team of over 90 engineers developing their internal interconnect, so the numbers can get much larger.
It is possible to make an interconnect IP for less but then but the result is a narrow, inflexible, hard-to-configure solution that cannot compete with interconnect solutions proven on hundreds of designs.
Internal interconnect development: Blinders are worse than budgets
Even if a company has the extensive resources to create its own internal interconnect IP, the internal engineers have a narrow view of their market because they only see their own company’s designs. It is not only a problem of budgets, it is a problem of application vision. If you only see a sliver of the market, you get blindsided as new SoC market opportunities emerge and you have scramble to adapt the existing technology or abandon it and start all over again. Over several product generations, this narrow development approach often leads to several incompatible version of the internal interconnect which impacts productivity, IP reuse and time to market. Such problems can be very costly in cash as well as the cost of all the lost opportunities these engineers could have been working on instead.
Another issue is assembling the right skill levels to build a competitive interconnect IP. You not only have to understand processor and SoC architectures but have to be good at EDA tool development, verification and application architectures. This set of skills is not easy to assemble and is not easy to keep together for the years of time it requires to achieve a proven and mature solution. Most companies are not simultaneously good at hardware design, EDA development, verification and system-level applications. Interconnect IP development is a multi-disciplinary team sport.
Mature commercial interconnect IP is the only logical option
Since only the largest semiconductor companies can afford the time, knowledge and investment to develop NoC-type interconnect IP internally, most companies are best served by adopting a horizontal commercial interconnect IP solution that leverages industry-wide experience and protocol standards.
The next time someone approaches a semiconductor general manager with a proposal to develop interconnect IP over a weekend with less than 10 people, it should be viewed with a healthy dose of skepticism. The world is littered with failed semiconductor projects that relied on a SoC interconnect that did not enable the necessary power, performance, cost or time to market required for success. The bottom line is that the interconnect is much more than just wires.