English
Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
Agile Design for Hardware, Part II
David Patterson and Borivoje Nikolić, UC Berkeley
EETimes (7/30/2015 07:00 AM EDT)
In the second of a three-part series, two Berkeley professors suggest its time to apply Agile design techniques to hardware.
We asked readers of Part I to guess the cost of a prototype run of 28 nm chips, as Agile development relies on a sequence of interim prototypes versus the One Big Tapeout of the traditional Waterfall process. Here are the results:
The surprisingly low manufacturing cost of prototype chips—one fifth the readers’ estimate—means Agile development is eminently affordable, even for academics. (See www.AgileSoC.com for more evidence.) It also calls into question the current high cost of designing SoCs using the Waterfall process. Having established Agile’s viability, based on our experience we propose four guidelines to lower development costs.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Agile Design for Hardware, Part I
- Is Agile coming to Hardware Development?
- Dealing with automotive software complexity with virtual prototyping - Part 2: An AUTOSAR use case
- Optimizing embedded software for power efficiency: Part 2 - Minimizing hardware power
- Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- PCIe error logging and handling on a typical SoC
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)