Gourav Kapoor, Babul Anunay, Anurag Jinda, Amol Agarwal (Freescale Semiconductors Pvt. Ltd)
Present-day System-on-Chips consist of a number of clock domains with different functional sources. Without lockup elements, it would have been impossible to stitch together all these in a single scan-shift setup for testing purpose. Lockup elements help us get rid of timing problems arising due to either of uncontrolled clock skew/uncommon clock path or both. In addition, as will be discussed later, lockup elements present a very simple method to provide robustness to scan chains against failures by providing additional margins in terms of hold timing. Either of the latch or flop can be used as a lockup element. This paper covers all such lockup scenarios with latch and register elements and discusses their merits and de-merits.
Lockup latch: A lockup latch can be inserted both in the launching and capturing domain. The polarity of course will have to be taken care of based on the physical feasibility to insert the latch in that domain.
Figure 1 : Hold critical positive skew path
Figure 1 above shows a hold critical positive skew path. While a physical solution would be to insert buffers in the data path which would in turn create issues in meeting timing across Process-Voltage-Temperature variations, this can also be tackled architecturally in following ways by inserting elements in launching/capturing domains.
Figure 2: positive lock up latch insertion in capture domain
Figure 3: negative lockup latch insertion in launch domain
Figure 2 and 3 show how lock up insertion relaxes the critical hold timing. It must be noted that the lockup element must be balanced with the flop of the domain in which it is placed.
Lockup register: Lockup registers required in scenarios where it is not desirable to tap/disturb the clock of either start point or endpoint due to any reason and the lockup needs to be inserted in a third physical domain. The physical requirement of balancing is not present in these cases. So, why not always use the lockup register instead if area constraint is not there? To explain this we will re-visit the shift-capture waveforms and illustrate the various timing scenarios with both latch and register as lockup element.
Shift-Capture with Lockup latch Element:
Figure 4: positive flop-positive lockup latch-positive flop
Figure 4 above shows the shift-atspeed capture-shift waveforms with latch present as lockup element.
S1 and s3 denote the setup check from the previous flop to the intermediate lockup element path. S2 and s4 denote the setup check from the intermediate lockup element to the next flop path. The setup check s2 is of interest here. Since the scan enable is already down to zero by the time the data reaches the capture edge, the check is rendered irrelevant. By extension the check s1 is also nullified. So it seems that we might not have to meet the atspeed half cycle (with time borrowing) setup check s1 to the latch. However that is not true. Consider the check s4 where although the data has a long time to reach the capture edge; but the latch, being positive, is not transparent during this time. So, if the atspeed half cycle (with time borrowing) setup check s3 is not met, meta-stability occurs which is passed on during check s4 for shifting out. Thus the critical half cycle timing to positive level sensitive latch is to be met here.
Let us take another example here to explain the case further:
Figure 5: positive flop-positive lockup latch-negative flop
Figure 5 above differs from Fig 4 in the sense that the final capture domain flop is negative edge triggered here. While this might not be a typical hold-driven requirement since the hold check was already half cycle before the lockup was introduced, this helps illustrate a unique timing scenario. Note that here the critical setup timing from the lockup latch to the negative flop is to be met here since scan enable is not yet down to zero. By extension, the setup check to the positive level sensitive latch is also to be met.
Shift-Capture with Lockup Register Element:
Let us now compare the Fig 5 scenario with the lockup element replaced by a register.
Figure 6: positive flop-positive lockup register-negative flop
In Figure 6 above, note that though the check from the lockup element is still valid, the other check to the lockup element is no longer applicable since the launch edge for that timing was present long earlier and data has a lot of time to reach destination in time.
This creates the perception that timing is more relaxed when registers are used as lockup elements but this does not turn out to be the case when all combinations are checked. When the lock element is sensitive to negative levels/edges the latch has an advantage over the register as a lockup element.
Figure 7 : positive flop-negative lockup latch-positive flop
Figure 8 : positive flop-negative lockup register-positive flop
Figure 7 and 8 illustrate that while the setup check to the latch is not required to be met to a negative level sensitive lockup latch (which remains transparent for a long time from the second capture pulse to the first shift edge), the requirement is present in a negative level triggered lockup register.
Below table captures atspeed setup timing requirement to and from the latch for all possible combinations:
Normally, positive register is not followed by a negative register in a scan chain because both the sequential elements will be unintentionally crossed in a single shift pulse. However, wherever present, the above FALSE paths can be marked as exceptions (for setup timing only) while meeting atspeed timing to and from the lockup elements which enables smoother and accurate timing closure of the atspeed test modes.