By Mandeep Singh, Amitav Halder (Freescale Semiconductor)
In present day’s situation, whenever we are in the phase of designing a cluster SoC, we have no reliable way of verifying our design in real case scenarios, or showcase the possibilities of our design through any demos. This, sometimes, paves way for critical design bugs which requires re-spins/cuts.
Rendering a video through a design is very easy at Post-Silicon level, as we have proper display to visualize the images and a camera feeding the SoC with the real-time live images. Though the same can be replicated in RTL verification, it would take weeks to run, hogging up resources, and abort eventually in a few days’ time. Pre-Silicon Emulation platform can fill this gap owing to its faster run time and traceability.
Our motivation was to render a video in multimillion gate display cluster SoC during RTL design cycle. Verification can check for limited data path sanity but other complex parameters like interoperability at different modes, bandwidth utilization etc. can only be gathered through volume of data.
The need of the hour is not just to have basic data connectivity checks but also complex performance benchmarking to deliver a well proven silicon before customer delivery. This flow with Emulation adds to success story.
RTL verification FLOW
- Legacy verification flow is based on data sanity. A hex file is used as an input to Video Interface Unit (VIU) & an output file generated from C-model is compared with the Display Controller (DCU) output. The path shown in the picture below takes almost a complete day to finish.
- Even though this approach can be used for basic data path checks , but not suitable for random image inputs, random selection of modes and other SOC level parameters, thus leading to non-satisfactory coverage. Apart from this, some other limitations are mentioned below.
- Time consuming
- Multiple images - it would take weeks to run, hogging up resources, and abort eventually in a few days’ time
- Use case, or Application testing not possible
Our aim is to enable various teams to work on the Video subsystem much before the Silicon is out, and catch bugs earlier in the design cycle, thus saving time, effort and money. The closest way to replicate this behavior is through Emulation Platform.
Key Advantages of Emulation over Traditional RTL Simulation Environment
- Faster run time
- Good observability and controllability
- Advanced interactive runtime debug with dynamic probes and events
- Support for Use case, and Application development
EMULATION PLATFORM: REQUIREMENTS, DATA FLOW
The primary intent was to have a completely automated, easily portable setup for testing continuous frames in the data path already verified in the RTL Verification environment, which could work even without debugger intervention. This would mean a complete reuse of tests generated in verification environment, loaded onto Emulator from backdoor. Now the question was “How to continuously load images onto design and trigger wave dump on a particular combination of signals (output frames) to analyze the design behavior”. The solution to the problem was found in a seldom used Self-Test Bench Emulation (STB) mode of Emulation. The traditional way of using STB mode, which is used to dump larger traces of waves, was improvised to create a solution for the problem at hand.
The basic data flow is shown in the diagram below:
Motion picture (Video) was seen on Emulation platform much before the silicon arrival. Though such solutions exist for FPGA, but synthesizing as big a design and covering a long data path with multiple modules simultaneously interacting with each other seemed next to impossible. This is an automated solution which is scalable across SoCs irrespective of their huge design size and multi module interactions.
Using Emulation proved beneficial over the traditional way of verification due to the following:
- Catch and fix compatibility issues between graphics subsystem modules early in the design phase, like endianness, swapping etc. owing to the ability of randomization of inputs, and parameters which won’t let anything escape.
- Catch bandwidth and contention issues when rendering images back to back as in real life scenarios. Design can be stressed to find corner cases, which earlier, could only be found in Post-Silicon validation.
- Help in development of software applications in early stages of design, and allow developers to showcase demos to Customers. This can not only enhance customer confidence on the quality of product but also also help save time that would go in stabilizing the application on silicon.
A frame of 720 x576 took 16 hrs in RTL Simulation environment, which would mean a requirement of 16*(25*30) = 12000Hrs for a 25 sec motion picture at 30 fps. Sounds impossible isn’t it? The same test was run on emulator within 4 hours, thereby saving 11996 Hours. The time reduction was by a factor of 3000.