By Babul Anunay, Ateet Mishra, Ashish Goel (Freescale Semiconductors Pvt. Ltd)
With the increasing complexity of design in today’s fast changing world, the thrust on power saving has increased manifold. Consequently, gating the most toggling signal on the SoC i.e. the clock has become the norm now rather than an exception. From timing perspective, clock gating brings some challenges and some special considerations. There are limitations to the automatic deduction of clock gating checks in a design by an EDA tool since there are cases where design dependency is involved. In the event of such a scenario, the detail understanding of clock gating check is necessary for an STA Engineer. We will discuss the same here in this paper with the example of such a scenario: clock gating check as inferred and applied on clock path multiplexers.
Out of the many scenarios in which a multiplexer may be present in a clock path, the following two are most commonly found:
- Multiplexer used for clock selection / Input-based clock multiplexer
- Multiplexer used for frequency division / Select-based clock multiplexer
Multiplexer used for clock selection / Input-based clock multiplexer
Figure 1 : Multiplexer used for Clock Selection
Figure 1 above shows a multiplexer being used for clock selection which we will also be referring to as Input-based clock multiplexer. As shown in the figure, both the inputs have clocks coming to it. The ENABLE pin switches the output from one clock to another. While switching from one clock to another, it must be taken care by design that the clocks don’t have an overlapping period of activity i.e. clock being switched to should be off while switching and should be turned on only when the switching is complete. If this architectural requirement is not taken care of, there are chances of glitches appearing for which certain timing conditions needs to be met. To ensure glitch-free transition at the output of the multiplexer, clock gating checks need to be met at the inputs. However, there is a design-dependency when applying clock gating checks on this multiplexer which we will be explaining below.
Figure 2 : CLK_D1 Inactive state 0
Figure 2 above shows the clock gating scenarios when the ENABLE toggles both in HIGH state of CLK_D0 and in the LOW state of CLK_D0. Glitches appear in the resulting waveform of the GATED_CLK in the former case while they are suppressed in the latter case suggesting the AND Gate type behavior of the Multiplexer. However this is not the case as another consideration on CLK_D1 remains.
Figure 3 : CLK_D1 Inactive state 1
Figure 3 differs from Figure 2 in the inactive state of the CLK_D1. It is noteworthy that when the inactive state of CLK_D1 is 1, the glitches appear when the ENABLE is toggling in the LOW state of CLK_D0 and not when in the HIGH state of CLK_D0. This behavior is opposite to what was observed when inactive state of CLK_D1 was 0. Thus to apply a clock gating check on such a multiplexer, the inactive state of the other input must first be ascertained.
Multiplexer used for frequency division / Select-based clock multiplexer
This brings us to our next clock path multiplexer: Multiplexer used for frequency division / Select-based clock multiplexer.
Figure 4 : Multiplexer used for Clock Division
Figure 4 shows a Multiplexer normally used for clock division. Note that the clock is passing through select pin with inputs EN_D0 and EN_D1 providing the enables for required division factor. The following figures will explain the application of clock gating checks for EN_D0 and EN_D1 pins.
Figure 5 : EN_D0 toggles with EN_D1 0
Figure 5 shows the behavior of the multiplexer output when EN_D0 toggles in LOW and HIGH values of Clock at select pin. Glitches are observed in the output waveform for the latter case and not the former suggesting an OR gate behavior. EN_D1 is assumed to be at 0 throughout. Unlike previous case though, in Figure 6, when EN_D1 is at 1 throughout, glitches are still observed in the same polarities. Thus appearance of glitches for toggling of END0 does not have a dependency on the polarity of EN_D1.
Figure 6 : EN_D0 toggles with EN_D1 1
Figure 7 and Figure 8 help us to conclude that for the case of EN_D1 toggling, the transitions must be made in the LOW value of the clock (AND gate type behavior) for glitch-free output. Again, this is irrespective of the state of the EN_D0 signal.
Figure 7 : EN_D1 toggles with EN_D0 0
Figure 8 : EN_D1 toggles with EN_D0 1
Figure 9 below shows the EN_D0 being launched from positive edge-triggered flop (indicative of its OR-type behavior) and EN_D1 being launched from negative edge-triggered flop showing AND type gating in architectural conformity with the above discussed reasons.
Figure 9 : Clock Gating on Divider Multiplexer
Thus suitable clock gating checks, as discussed in this paper, need to be applied on both the types of multiplexers frequently found in clock path of a design, by meeting which in STA we can ensure glitch-free clock outputs resulting in smooth and reliable functioning of the chip, a must-have requirement in crucial safety applications.