Randy Caplan, Silicon Creations
This presentation is about a problem we at Silicon Creations have seen quite often when our, or others’ PLLs are used in complex SoCs. Although the design team usually implements the PLL correctly in the chip with the right supplies connected the right ways, we have often seen that designers overlook the significant impact that their floorplan and power supply plan have on the clock as it travels from the PLL to the circuits the PLL is clocking. This is the impact of the SoCsupply noise on the quality of the clock. Because of this we have often helped our customers to understand this issue to ensure their chip works first time, or help them understand how to repair an SoCwhen they have made mistakes in the design. Our Application notes do include lots of guidelines for this, but we often have to explain this in person or over a WebEx session. Drawings and whiteboards are always helpful, and we’ve made a few short presentations in the past. For the forum today we decided to pull this material together to a presentation we think we will be useful to at least some of you.
The supply noise in SoCshurts the clock by creating jitter. This jitter is important because it reduces timing margin and can limit the speed of logic circuits or even cause them to fail. When the clock is used for SerDes the jitter can prevent the SerDes from operating as fast as it should. And the jitter can also be seen as distortion so that the SNR of clocked analog circuits is too low.
This presentation talks about jitter, the mechanism that causes this additional jitter on SoCs, how you can simulate this and what you can do about it.
If you wish to download a copy of this white paper, click here