Syed Shakir Iqbal , Mitul Soni & Gourav Kapoor (Freescale)
EDN (October 07, 2015)
With rising SoC design complexity, hierarchical backend design closure has become almost ubiquitous across the industry. Block and sub-block partitioning allow designers to exploit engineering and tool bandwidth more efficiently through optimized resource use. In addition, this approach is compatible with a bottom-to-top design approach.
This is in keeping with design practice wherein mature IP partitions are taken into the backend cycle while work is going on to finish the rest of the chip. Benefits like design-cycle reduction have prompted designers to push for multi-level partitioning schemes. However, as the level of hierarchical partitions increases, so do the challenges involved in their closure and signoff.
In this paper, we discuss the major timing and implementation challenges involved in multi-level hierarchical partitioning and modeling schemes.
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