Nalin Gupta, Mayank Verma and Nitin Bhardwaj (Freescale Semiconductor)
Lock-up Latches play an important role in fixing timing problems especially for hold timing closure. A lock-up latch is a transparent latch used to avoid large clock skew and mitigate the problem in closing hold timing due to large uncommon clock path. Lock-up latches are used in between the two scan flops having large hold failure probability due to uncommon clock path so that there is no issue in closing timing in a scan chain across domains in scan-shift mode.
From timing perspective lock-up latches can be the best solution to avoid large uncommon path between the clocks of two flops. But Lock-up latches are not always help; they can be the cause for congestion issue after scan stitching in designs containing both EDT and LBIST.
Lock-up Latch insertion during scan stitching:
1- Concatenation of Scan Chains of Different Clock Domains: When there is need of concatenation of scan chains of different clock domains Lock-up latch is inserted in order to mitigate large clock skew and uncommon path.
Fig.1: Lock-up Latch connecting two different Scan chains
2- Flops within same domain but are far apart to each other: When flops are sitting far apart but within the same clock domain, so to avoid large clock skew and uncommon path lock-up latch is inserted in between.
Fig.2 Lock-up Latch connecting far apart flops within same clock domain
Issues due to Lock-up Latch insertion:
Lock-up latches on the scan path act as “break points” across which flops cannot be reordered.
Due to lock-up latch on scan path, tool is not able to improve the chain length by reordering in an efficient manner.
Whenever there is a lock-up latch in the chain, the scan chain is broken into two smaller segments. These segments in turn have their own start-end points which are fixed and cannot be reordered. This results in longer scan chain wire length.
Poor Scan reordering substantially increases the length of scan chain and hence the congestion which unnecessary increases the capacitance of scan flops outputs i.e.more loading of Q pin which leads to more chip power dissipation.
All these issues give rise to one major issue that is Congestion.
Role of Lock-up Latches in Congestion:
Lock-up latches inserted on scan paths limit the reordering capability, so the chains which are supposed to get short in terms of scan chain wire length get restricted due to these “break points”. Lock-up latches between two flops which are far apart within the same scan chain and same clock domain breaks the chain in two smaller segments. These break points don’t allow scan reordering and efficient chain length improvement, hence the long wire length and criss-crossing of chains results in congestion.
When there is stitching of flops with memories, tool inserts the lock-up latches in such a way that the chain gets stitched in haphazard manner with long scan chain wire length causing congestion issue in the design.
When there is a lock-up latch just before the last element in the chain, it breaks the chain in two and the information for last flop doesn’t get dumped in Scan def. When scan def is read in EDA tool just because lack of information for the last flop, reordering of scan chains doesn’t happen correctly and Lock-up latch sits anywhere in the design.
In LBIST we keep many but small scan chains normally with scan chain length in the range of ~50.This is to reduce the runtime of LBIST on-field run. As these many small chains are spread apart, it may happen that these chains get stitched with flops from different clock domains resulting in a large number of lock-up latches getting inserted. These chains are connected to the LBIST controller whose placement is influenced by the connections it makes to these chains. Due to lock-up latch insertion, reordering of scan chains doesn’t happen and the start and stop elements of a chain are not allowed to sit together resulting in sub-optimal placement of LBIST controller which in turn aggravates the design Congestion.
Fig3. Criss-Crossing due to Lock-up latch insertion in scan chain
Approaches to avoid large number of lock-up latch insertion:
Use max chain limit for scan stitching in such a way that the need of stitching any extra flop from other clock domain to ensure the max limit requirement should not get raised.
For the reason stated above, designs using multibit flops should ensure not to use an odd number of maximum chain length limit.
Connect scan chains with physical information so that the flops sitting far apart to each other should not get stitched.
After using above mentioned approaches there will be no inter and intra Criss-crossing of scan chains
Fig4.: No Criss-crossing due to absence of lock-up latches “break-points”
Lock-up latches can be the savior in hold timing closure, but can play pivotal role in congestion issues.
Congestion issue can be reduced by using physical aware scan stitching techniques and redefining the max chain limit for scan chains.
If you wish to download a copy of this white paper, click here