K. Charles Janac, President and CEO, Arteris
EETimes (10/30/2015 10:06 AM EDT)
Chip designs are becoming so complex that they are extremely difficult to implement in the physical design stage. Predicting trouble spots beforehand is paramount.
Whether Moore’s Law is still valid or not, there is little argument that semiconductor design is becoming more complex. In the race to adopt 16/14nm FinFET designs, we sometimes fail to see the ramifications of physical design constraints on logic design. In particular, most of the SoC wires that connect various IPs and subsystem blocks are contained in the interconnect IP. In modern designs, choices made in the interconnect IP design not only effect the SoC architecture but also physical design.
The need for physically aware IP
In an industry where time-to-market is of critical importance, our chip designs are becoming so complex that they are extremely difficult to implement in the physical design stage. If only we could predict trouble spots beforehand, perhaps we could avoid the pitfalls in the backend of the process. To do this, we need to make interconnect IP design physically aware to address to complexity and cost of sub-28nm SoC projects. This can be done by applying EDA techniques to leverage network on chip interconnect IP RTL hardware already used in many of the world’s highest volume advanced SoC designs.
One of the challenges is to easily allow architects to visualize the physical design implications of their architecture choices. SoC architectures that do not take into account physical considerations can lead to serious problems. One relatively recent example of failing to consider physical design implications was a complex gaming chip with an architecture that was so difficult to route that it forced the rework of the SoC topology. This rework delayed the project so much that the chip missed a major market window and incurred a $200M loss.
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